Structures and methods of fabricating dual gate devices
First Claim
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1. A method of fabricating a dual gate semiconductor device, said method comprising:
- depositing oxide into a first trench and into a second trench that are formed in a substrate, said oxide also deposited over a mesa that is between said first trench and said second trench;
depositing first polysilicon into said first trench and into said second trench;
performing a first polysilicon polishing process to planarize the exposed upper surfaces of said first polysilicon so that, after said first polysilicon polishing process, exposed surfaces of said first polysilicon are flush with the surface of said oxide;
after said polysilicon polishing process, performing an oxide polishing process to remove said oxide from over said mesa and further remove part of said first polysilicon so that, after said oxide polishing process, exposed surfaces of said first polysilicon are flush with said mesa;
after said first polysilicon polishing process, forming a third trench in said substrate between said first and second trenches, wherein said third trench is shallower than said first and second trenches;
depositing second polysilicon into said third trench;
performing a second polysilicon polishing process to planarize an exposed surface of said second polysilicon so that said surface is flush with adjacent surfaces; and
forming a first metal contact to said first polysilicon and a second metal contact to said second polysilicon.
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Abstract
First polysilicon (poly-1) is deposited into deep trenches that have been formed in a substrate. A first polysilicon polishing process is performed to planarize the exposed surfaces of the poly-1 so that the surfaces are flush with adjacent surfaces. Then, shallow trenches are formed in the substrate between the deep trenches, and second polysilicon (poly-2) is deposited into the shallow trenches. A second polysilicon polishing process is performed to planarize the exposed surface of the poly-2 so that the surface is flush with adjacent surfaces. Metal contacts to the poly-1 and the poly-2 are then formed.
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Citations
17 Claims
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1. A method of fabricating a dual gate semiconductor device, said method comprising:
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depositing oxide into a first trench and into a second trench that are formed in a substrate, said oxide also deposited over a mesa that is between said first trench and said second trench; depositing first polysilicon into said first trench and into said second trench; performing a first polysilicon polishing process to planarize the exposed upper surfaces of said first polysilicon so that, after said first polysilicon polishing process, exposed surfaces of said first polysilicon are flush with the surface of said oxide; after said polysilicon polishing process, performing an oxide polishing process to remove said oxide from over said mesa and further remove part of said first polysilicon so that, after said oxide polishing process, exposed surfaces of said first polysilicon are flush with said mesa; after said first polysilicon polishing process, forming a third trench in said substrate between said first and second trenches, wherein said third trench is shallower than said first and second trenches; depositing second polysilicon into said third trench; performing a second polysilicon polishing process to planarize an exposed surface of said second polysilicon so that said surface is flush with adjacent surfaces; and forming a first metal contact to said first polysilicon and a second metal contact to said second polysilicon. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of fabricating a dual gate semiconductor device, said method comprising:
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forming a first trench and a second trench in a substrate, said first and second trenches separated by a first mesa; forming a first oxide layer inside said first and second trenches and over said first mesa, and then depositing first polysilicon into said first and second trenches; performing a first polysilicon polishing process to remove at least some of said first polysilicon; after said first polysilicon polishing process id performed, etching back the exposed upper surface of said first polysilicon so that it is recessed relative to said first oxide layer over said first mesa; after said etching, performing an oxide polishing process to remove said first oxide layer from over said first mesa and any portion of said exposed upper surface of said first polysilicon protruding above said first mesa so that, after said oxide polishing process is performed, exposed surfaces of said first polysilicon are flush with said first mesa; after said first polysilicon polishing process and after said oxide polishing process are performed, forming a third trench in said first mesa between said first and second trenches, said first and third trenches separated by a second mesa and said second and third trenches separated by a third mesa, wherein said third trench is shallower than said first and second trenches; forming a second oxide layer inside said third trench and over said second and third mesas, and then depositing second polysilicon into said third trench; and performing a second polysilicon polishing process to remove at least some of said second polysilicon. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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Specification