Semiconductor device

• US 9,577,108 B2
• Filed: 05/19/2014
• Issued: 02/21/2017
• Est. Priority Date: 05/21/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Endo, Yuta, Sasaki, Toshinari, Noda, Kosei, Sato, Mizuho
• Primary Examiner(s): Gumedzoe, Peniel M
• Assistant Examiner(s): Johnson, Christopher
• Application Number:
  US14/281,031
• Publication Number:
  US 20140252347A1
• Time in Patent Office: 1,009 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

Disclosed is a semiconductor device with a transistor in which an oxide semiconductor is used. An insulating layer on a back channel side of the oxide semiconductor layer has capacitance of lower than or equal to 2×10⁻⁴ F/m². For example, in the case of a top-gate transistor, a base insulating layer has capacitance of lower than or equal to 2×10⁻⁴ F/m², whereby the adverse effect of an interface state between the substrate and the base insulating layer can be reduced. Thus, a semiconductor device where fluctuation in electrical characteristics is small and reliability is high can be manufactured.

Claims

1. A method of manufacturing a semiconductor device comprising the steps of:

forming an insulating layer over a substrate;

forming an oxide semiconductor layer over and in contact with the insulating layer;

forming an island shape oxide semiconductor layer by etching the oxide semiconductor layer;

heating the island shape oxide semiconductor layer in an inert gas in a first period and then in an oxidizing gas in a second period after the first period; and

forming a gate electrode over the island shape oxide semiconductor layer,

wherein the insulating layer has a thickness in which capacitance per unit area is lower than or equal to 2×

10<sup>−

4</sup> F/m² by capacitance, and

wherein the oxide semiconductor layer is formed by sputtering with a temperature of the substrate kept 150°

C. or higher.

2. The method according to claim 1, wherein the insulating layer comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, and aluminum nitride.

3. The method according to claim 1, wherein the insulating layer comprises multiple layers, wherein one of the multiple layers which is in contact with the oxide semiconductor layer is an oxide layer.

4. The method according to claim 1, wherein the oxide semiconductor layer comprises indium, zinc and gallium.

5. The method according to claim 1, wherein the insulating layer comprises a first layer and a second layer over the first layer, the first layer comprising aluminum oxide, and the second layer comprising silicon oxynitride or silicon oxide.

6. The method according to claim 1, wherein the substrate is a glass substrate.

7. A method of manufacturing a semiconductor device comprising the steps of:

forming an insulating layer over a substrate;

forming an oxide semiconductor layer over and in contact with the insulating layer;

forming an island shape oxide semiconductor layer by etching the oxide semiconductor layer;

heating the island shape oxide semiconductor layer in an inert gas in a first period and then in an oxidizing gas in a second period after the first period; and

forming a gate electrode over the island shape oxide semiconductor layer,

wherein the insulating layer has a thickness in which capacitance per unit area is lower than or equal to 2×

10<sup>−

4</sup> F/m² by capacitance.

8. The method according to claim 7, wherein the insulating layer comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, and aluminum nitride.

9. The method according to claim 7, wherein the insulating layer comprises multiple layers, wherein one of the multiple layers which is in contact with the oxide semiconductor layer is an oxide layer.

10. The method according to claim 7, wherein the oxide semiconductor layer comprises indium, zinc and gallium.

11. The method according to claim 7, wherein the insulating layer comprises a first layer and a second layer over the first layer, the first layer comprising aluminum oxide, and the second layer comprising silicon oxynitride or silicon oxide.

12. The method according to claim 7, wherein the substrate is a glass substrate.