Method to form a 3D semiconductor device

• US 9,577,642 B2
• Filed: 11/07/2010
• Issued: 02/21/2017
• Est. Priority Date: 04/14/2009
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Wurman, Ze'ev
• Primary Examiner(s): Richardson, Jany
• Application Number:
  US12/941,074
• Publication Number:
  US 20120193806A1
• Time in Patent Office: 2,298 Days
• Field of Search: 257/E21.506, 257/E25.013, 257/E25.017, 257/685, 257/686, 257/690, 257/691, 257/698, 257723-725, 257/777, 326 37- 41, 326/47
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters

Abstract

A method to form a 3D integrated circuit, the method including: fabricating two or more devices; connecting the devices together to form the 3D integrated circuit, where at least one of the devices has at least one unused designated dice line and at least one of the devices is a configurable device; and interconnecting at least two of the devices using Through Silicon Vias.

Claims

1. A method to form a 3D integrated circuit, the method comprising:

fabricating two or more devices;

connecting the devices together to form the 3D integrated circuit,

wherein at least one of said devices has at least one unused designated dice line and at least one of said devices is a configurable device; and

interconnecting at least two of the devices using Through Silicon Vias,

wherein said designated dice line is part of a plurality of designated dice lines designed to allow choice of amount of logic or memory or input/output cells for said at least one of said devices.

2. The method of claim 1, further comprising:

forming a plurality of Micro-Controller-Units (MCUs) within said configurable device,

wherein at least one of said plurality of Micro-Controller-Units comprises connections to configure at least one porting of said configurable device.

3. The method of claim 1, further comprising:

forming a base device, and

horizontally stacking said two or more devices above the base device.

4. The method of claim 1,

wherein said configurable device is a configurable logic device and another one of said two or more devices comprises Input-Output circuits to connect said 3D integrated circuit to external devices.

5. The method of claim 1,

wherein one of said two or more devices is a configurable logic device and another one of said two or more devices comprises configurable Input-Output circuits to connect said 3D integrated circuit to external devices.

6. The method of claim 1, further comprising:

constructing at least a first 3D integrated circuit and a second 3D integrated circuit,

wherein said first 3D integrated circuit comprises a first device and a second device,

wherein said second 3D integrated circuit comprises a third device and a fourth device,

wherein said first device functionality is substantially similar to said third device functionality, and said second device functionality is substantially different from said fourth device functionality.

7. The method of claim 1,

wherein one of said two or more devices is a configurable logic device and another one of said two or more devices comprises configurable memories circuits.

8. A method to form a 3D integrated circuit, the method comprising:

fabricating two or more devices;

connecting the devices together using Through Silicon Vias to form the 3D integrated circuit; and

forming dice lines for at least one of said two or more devices by a second etch of circuit patterns previously defined by a first etch,

wherein said forming dice lines is designed to allow choice of amount of logic or memory or input/output cells for said at least one of said two or more devices.

9. The method of claim 8,

wherein said circuit patterns comprise transistors or metal interconnect.

10. The method of claim 8, further comprising:

forming a base device, and

horizontally stacking said two or more devices above said base device.

11. The method of claim 8,

wherein one of said two or more devices is a configurable logic device and another one of said two or more devices comprises Input-Output circuits to connect said 3D integrated circuit to external devices.

12. The method of claim 8,

wherein one of said two or more devices is a configurable logic device and another one of said two or more devices comprises configurable Input-Output circuits to connect said 3D integrated circuit to external devices.

13. The method of claim 8, further comprising:

forming a plurality of Micro-Controller-Units (MCUs) within a configurable device,

wherein at least one of said plurality of Micro-Controller-Units comprises connections to configure at least one porting of said configurable device, and

wherein one of said two or more devices is said configurable logic device.

14. The method of claim 8,

wherein one of said two or more devices is a configurable logic device and another one of said two or more devices comprises configurable memories circuits.

15. A method to form a first and a second 3D integrated circuit, the method comprising:

fabricating a first and a second device and connecting said first device to said second device using Through Silicon Vias;

fabricating a third and a fourth device and connecting said third device to said fourth device using Through Silicon Vias;

wherein a majority of a first set of masks used for forming said first device are the same as a majority of a second set of masks used for forming said third device, and

wherein said first device has a significantly larger area than said third device, and

wherein said first device has significantly more logic or memory or input/output cells than said third device.

16. The method of claim 15,

wherein said devices comprise circuit patterns, and

wherein said circuit patterns comprise transistors or metal interconnect.

17. The method of claim 15, further comprising:

forming a base device, and

horizontally stacking said first device and said second device above said base device.

18. The method of claim 15,

wherein said first device is a configurable logic device and said second device comprises Input-Output circuits to connect said first 3D integrated circuit to external devices.

19. The method of claim 15,

wherein said first device is a configurable logic device and said second device comprises configurable Input-Output circuits to connect said first 3D integrated circuit to external devices.

20. The method of claim 15, further comprising:

forming a plurality of Micro-Controller-Units (MCUs) within a configurable device,

wherein at least one of said plurality of Micro-Controller-Units comprises connections to configure at least one porting of said configurable device, and

wherein at least one of said devices is said configurable device.