Efficient processing and detection of balanced codes

• US 9,577,664 B2
• Filed: 08/08/2016
• Issued: 02/21/2017
• Est. Priority Date: 05/20/2010
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Tajalli, Armin, Cronie, Harm, Shokrollahi, Amin
• Primary Examiner(s): LAUTURE, JOSEPH J
• Application Number:
  US15/231,342
• Publication Number:
  US 20160352354A1
• Time in Patent Office: 197 Days
• Field of Search: 341/58, 341/95, 375/295, 375/296, 375/259, 375/134, 714/776, 714/18, 714/787, 714/755
• US Class Current: 1/1
• CPC Class Codes: G11B 20/1426 conversion to or from block codes or representations thereof
• CPC Class Codes: H03F 1/3247 using feedback acting on predistortion circuits H03F1/3264 takes precedence
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor
• CPC Class Codes: H03M 13/2957 Turbo codes and decoding
• CPC Class Codes: H03M 5/14 Code representation, e.g. transition, for a given bit cell depending on the information in one or more adjacent bit cells, e.g. delay modulation code, double density code
• CPC Class Codes: H04B 1/7156 Arrangements for sequence synchronisation
• CPC Class Codes: H04B 3/54 Systems for transmission via power distribution lines
• CPC Class Codes: H04L 1/0003 by switching between different modulation schemes
• CPC Class Codes: H04L 1/0048 in conjunction with detection of multiuser or interfering signals, e.g. iteration between CDMA or MIMO detector and FEC decoder for spatial equalizer H04L25/03286
• CPC Class Codes: H04L 1/0053 specially adapted for power saving
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/0059 Convolutional codes

Abstract

Circuits that are matched to balanced codes may recover transmitted information in a noise resilient and power efficient manner. Circuit components for processing a balanced code may include one or more of: matched amplification of the signals representing the balanced code, matched equalization and/or filtering on the signals representing the balanced code, matched non-linear filtering on the signaling representing the balanced code to detect the presence of particular symbols and matched latching of the signals representing the balanced code. Such matched circuits and circuit components may be achieved at least in part by incorporating suitable common circuit nodes and/or a single energy source into circuit topologies.

Claims

1. An apparatus comprising:

a pair of circuit branches comprising a first circuit branch and a second circuit branch the pair of circuit branches arranged in a differential amplifier configuration, each circuit branch comprising one or more transistors connected in parallel, each transistor having an input connected to a wire of a multi-wire bus and configured to receive a symbol of a balanced codeword from the connected wire, wherein at least one of the circuit branches comprises at least two transistors receiving different symbols of the balanced codeword;

each circuit branch further comprising a load impedance, connected in series with the one or more transistors of the corresponding circuit branch;

a current source connected to the pair of circuit branches, the current source having a fixed current magnitude, the current source configured to draw currents through the one or more transistors and load impedance of each of the pair of circuit branches; and

a differential amplifier output node having a differential voltage output signal formed by the load impedances, the differential voltage output signal having one of two values equal in magnitude and opposite in sign, wherein the sign of the value of the differential output signal is used to identify one or more output bits.

2. The apparatus of claim 1, wherein a first wire of the multi-wire bus is connected to all of the one or more transistors in the first circuit branch of the pair of circuit branches, and all remaining wires of the multi-wire bus are connected to a corresponding transistor in the one or more transistors in the second circuit branch.

3. The apparatus of claim 2, wherein the one or more transistors in each circuit branch are NMOS transistors, and wherein the differential voltage output signal identifies if the first wire connected to all of the one or more transistors in the first circuit branch is a maximal element.

4. The apparatus of claim 2, wherein the one or more transistors in each circuit branch are PMOS transistors, and wherein the differential voltage output signal identifies if the first wire connected to all of the one or more transistors in the first circuit branch is a minimal element.

5. The apparatus of claim 1, wherein the first circuit branch is configured to apply a weight to a corresponding symbol of the balanced codeword.

6. The apparatus of claim 5, wherein the one or more transistors in the first circuit branch comprises two or more transistors, and wherein the first circuit branch is configured to apply the weight to the symbol of the balanced codeword by connecting the two or more transistors to a wire of the multi-wire bus associated with the corresponding symbol of the balanced codeword.

7. The apparatus of claim 5, wherein the first circuit branch is configured to apply the weight to the corresponding symbol of the balanced codeword by connecting a wire of the multi-wire bus associated with the corresponding symbol of the balanced codeword to a transistor having different transistor characteristics than at least one transistor in the second circuit branch of the pair of circuit branches.

8. The apparatus of claim 1, wherein the balanced codeword is part of an at least ternary balanced code.

9. The apparatus of claim 1, wherein the balanced codeword is a balanced permutation-modulation (PM) codeword.

10. The apparatus of claim 9, wherein the balanced PM codeword is a permutation of a vector:

[1,1,1, −

1, −

1, −

1].

11. A method comprising:

receiving symbols of a balanced codeword at a pair of circuit branches comprising a first circuit branch and a second circuit branch arranged in a differential amplifier configuration, each circuit branch comprising one or more transistors connected in parallel, each symbol received at an input of a transistor, wherein at least one of the circuit branches comprises at least two transistors receiving different symbols of the balanced codeword;

drawing currents through the one or more transistors of each branch using a current source connected to the pair of circuit branches, the current source having a fixed current magnitude; and

forming a differential voltage output signal using a pair of load impedances, each circuit branch connected to a corresponding load impedance, the differential voltage output signal formed by drawing currents through the pair of load impedances, the differential voltage output signal having one of two values equal in magnitude and opposite in sign, wherein the sign of the value of the differential output signal is used to identify one or more output bits.

12. The method of claim 11, wherein a first wire of the multi-wire bus is connected to all of the one or more transistors in the first circuit branch of the pair of circuit branches, and all remaining wires of the multi-wire bus are connected to a corresponding transistor in the one or more transistors in the second circuit branch.

13. The method of claim 12, wherein the one or more transistors in each circuit branch are NMOS transistors, and wherein the differential voltage output signal identifies if the first wire connected to all of the one or more transistors in the first circuit branch is a maximal element.

14. The method of claim 12, wherein the one or more transistors in each circuit branch are PMOS transistors, and wherein the differential voltage output signal identifies if the first wire connected to all of the one or more transistors in the first circuit branch is a minimal element.

15. The method of claim 11, further comprising applying a weight to a corresponding symbol the balanced codeword.

16. The method of claim 15, wherein applying the weight comprises connecting two or more transistors of the first circuit branch to a wire of the multi-wire bus associated with the corresponding symbol of the balanced codeword.

17. The method of claim 15, wherein applying the weight comprises connecting a transistor of the first circuit branch having different transistor characteristics than at least one transistor in the second circuit branch to a wire of the multi-wire bus associated with the corresponding symbol of the balanced codeword.

18. The method of claim 11, wherein the balanced codeword is part of an at least ternary balanced code.

19. The method of claim 11, wherein the balanced codeword is a balanced permutation-modulation (PM) codeword.

20. The method of claim 19, wherein the balanced PM codeword is a permutation of a vector:

[1,1,1, −

1, −

1, −

1].