Method of monitoring an optoelectronic transceiver with multiple flag values for a respective operating condition

• US 9,577,759 B2
• Filed: 11/09/2015
• Issued: 02/21/2017
• Est. Priority Date: 02/05/2001
• Status: Expired due to Term

• Current Assignee: II-VI Delaware, Inc. (Coherent Corp.)
• Original Assignee: Finisar Corporation (II-VI Incorporated)
• Inventors: Aronson, Lewis B., Hosking, Lucy G.
• Primary Examiner(s): Sedighian, M. R.
• Application Number:
  US14/936,642
• Publication Number:
  US 20160065309A1
• Time in Patent Office: 470 Days
• Field of Search: 398/135, 398/138
• US Class Current: 1/1
• CPC Class Codes: G01M 11/00 Testing of optical apparatus; Testing structures by optical methods not otherwise provided for
• CPC Class Codes: G01M 11/30 Testing of optical devices, constituted by fibre optics or optical waveguides
• CPC Class Codes: G01M 99/002 Thermal testing flaw detection G01N25/72
• CPC Class Codes: H04B 10/07 Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems
• CPC Class Codes: H04B 10/0799 Monitoring line transmitter or line receiver equipment
• CPC Class Codes: H04B 10/40 Transceivers
• CPC Class Codes: H04B 2210/08 Shut-down or eye-safety

Abstract

The circuit monitors operation of an optoelectronic transceiver that includes a laser transmitter and a photodiode receiver. The circuit includes analog to digital conversion circuitry configured to convert a first analog signal corresponding to a first operating condition of said optoelectronic transceiver into a first digital value, and convert a second analog signal corresponding to a second operating condition of said optoelectronic transceiver into a second digital value corresponding to a second operating condition. The circuit also includes a memory configured to store the first digital value in a first memory location that is mapped to a predefined and unique first address and to store the second digital value in a second memory location that is mapped to a predefined and unique second address. The circuit includes an interface configured to enable a host external to the optoelectronic transceiver to access the first digital value using the first address and to access the second digital value using the second address.

Claims

1. A circuit for monitoring operation of an optoelectronic transceiver, which includes a laser transmitter and a photodiode receiver, said circuit comprising:

analog to digital conversion circuitry configured to convert a first analog signal corresponding to a first operating condition of said optoelectronic transceiver into a first digital value, and convert a second analog signal corresponding to a second operating condition of said optoelectronic transceiver into a second digital value;

memory configured to store the first digital value in a first memory location that is mapped to a predefined and unique first address and to store the second digital value in a second memory location that is mapped to a predefined and unique second address; and

an interface configured to enable a host external to the optoelectronic transceiver to access the first digital value using the first address and to access the second digital value using the second address.

2. The circuit of claim 1, wherein the first digital value is selected from a group consisting of:

a supply voltage measurement, a laser temperature measurement, a laser wavelength measurement, and a thermoelectric cooler current measurement.

3. The circuit of claim 1, wherein the first digital value includes a supply voltage measurement.

4. The circuit of claim 1, wherein the first digital value includes a laser temperature measurement.

5. The circuit of claim 1, wherein the first digital value includes a laser wavelength measurement.

6. The circuit of claim 1, wherein the first digital value includes a thermoelectric cooler current measurement.

7. The circuit of claim 1, further comprising a processor configured to store the first digital value in the first memory location and to store the second digital value in the second memory location.

8. The circuit of claim 7, wherein the processor is further configured to access the first digital value in the first memory location and to access the second digital value in the second memory location.

9. The circuit of claim 8, wherein the processor is further configured to access the first digital value in response to receiving the first address from the host and to access the second digital value in response to receiving the second address from the host.

10. The circuit of claim 9, wherein the processor is further configured to provide the digital values accessed by the processor to the host via the interface.

11. The circuit of claim 1, wherein the circuit further comprises control circuitry configured to generate control signals to control operation of the optoelectronic transceiver in accordance with one or more of the first digital value and the second digital value.

12. The circuit of claim 1, wherein the circuit further comprises operation disable circuitry configured to disable operation of at least part of the optoelectronic transceiver in response to a signal, wherein the signal is based on one or more of the first digital value and the second digital value.

13. The circuit of claim 1, wherein the circuit further comprises rate selection circuitry configured to set the photodiode receiver to a bandwidth in response to a signal, wherein the signal is based on one or more of the first digital value and the second digital value.

14. A circuit for monitoring operation of an optoelectronic transceiver, which includes a laser transmitter and a photodiode receiver, said circuit comprising:

analog to digital conversion circuitry configured to convert a first analog signal corresponding to a first operating condition of said optoelectronic transceiver into a first digital values, and convert a second analog signal corresponding to a second operating condition of said optoelectronic transceiver into a second digital value;

memory configured to store the first digital value in a first memory location that is mapped to a predefined and unique first address and to store the second digital value in a second memory location that is mapped to a predefined and unique second address;

comparison logic configured to compare the first digital value with a first limit value to generate a first flag value and to compare the second digital value with a second limit value to generate a second flag value, wherein the first flag value is stored in a first flag memory location that is mapped to a predefined and unique first flag memory address and the second flag value is stored in a second flag memory location that is mapped to a predefined and unique second flag memory address, wherein the first flag memory address and the second flag memory address are known to a host external to the optoelectronic transceiver; and

an interface configured to enable the host to access the first digital value using the first address, to access the second digital value using the second address, to access the first flag value using the first flag memory address, and to access the second flag value using the second flag memory address.

15. The circuit of claim 14, further comprising a processor configured to store the first digital value in the first memory location, to store the second digital value in the second memory location, to store the first flag value in the first flag memory address, and to store the second flag value in the second flag memory address.

16. The circuit of claim 15, wherein the processor is further configured to access the first digital value in the first memory location, to access the second digital value in the second memory location, to access the first flag value in the first flag memory address, and to access the second flag value in the second flag memory address.

17. The circuit of claim 16, wherein the processor is further configured to access the first digital value in response to receiving the first address from the host, to access the second digital value in response to receiving the second address from the host, to access the first flag value in response to receiving the first flag memory address, and to access the second flag value in response to receiving the second flag memory address.

18. The circuit of claim 17, wherein the processor is further configured to provide the digital and flag values accessed by the processor to the host via the interface.

19. The circuit of claim 14, wherein the circuit further comprises control circuitry configured to generate control signals to control operation of the optoelectronic transceiver in accordance with one or more of the first flag value and the second flag value.

20. The circuit of claim 14, wherein the circuit further comprises operation disable circuitry configured to disable operation of at least part of the optoelectronic transceiver in response to a signal, wherein the signal is based on one or more of the first flag value and the second flag value.