Low-stress low-hydrogen LPCVD silicon nitride

• US 9,580,304 B2
• Filed: 05/07/2015
• Issued: 02/28/2017
• Est. Priority Date: 05/07/2015
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Dellas, Nicholas Stephen
• Primary Examiner(s): Gebreyesus, Yosef
• Application Number:
  US14/706,941
• Publication Number:
  US 20160325987A1
• Time in Patent Office: 663 Days
• US Class Current: 1/1
• CPC Class Codes: B81B 2203/0127 Diaphragms, i.e. structures separating two media that can control the passage from one medium to another; Membranes, i.e. diaphragms with filtering function
• CPC Class Codes: B81B 3/0072 For controlling internal stress or strain in moving or flexible elements, e.g. stress compensating layers
• CPC Class Codes: B81B 7/0022 Protection against electrostatic discharge electrostatic discharge protection for electronic semiconductor circuits H01L27/0248; circuit arrangements for protecting electronic switching circuits used for pulse technique against overcurrent or overvoltage H03K17/08
• CPC Class Codes: B81C 1/00666 Treatments for controlling internal stress or strain in MEMS structures
• CPC Class Codes: B81C 2201/0166 by ion implantation
• CPC Class Codes: B81C 2201/0177 Epitaxy, i.e. homo-epitaxy, hetero-epitaxy, GaAs-epitaxy
• CPC Class Codes: B81C 2201/0181 Physical Vapour Deposition [PVD], i.e. evaporation, sputtering, ion plating or plasma assisted deposition, ion cluster beam technology
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/3245 of AIIIBV compounds
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 23/291 Oxides or nitrides or carbides, e.g. ceramics, glass
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/778 with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface H01L29/803 takes precedence
• CPC Class Codes: H01L 29/7787 : with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Abstract

A microelectronic device contains a high performance silicon nitride layer which is stoichiometric within 2 atomic percent, has a low stress of 600 MPa to 1000 MPa, and has a low hydrogen content, less than 5 atomic percent, formed by an LPCVD process. The LPCVD process uses ammonia and dichlorosilane gases in a ratio of 4 to 6, at a pressure of 150 millitorr to 250 millitorr, and at a temperature of 800° C. to 820° C.

Claims

1. A method of forming a Gallium-Nitride Field Effect Transistor (GaN FET) device, comprising the steps:

forming a stack of gallium nitride and aluminum gallium nitride layers as a substrate;

forming a cap layer of gallium nitride on the stack;

forming a silicon nitride layer on a first surface of the cap layer using a low-pressure chemical vapor deposition (LPCVD) process, the silicon nitride layer having the following properties;

a silicon;

nitrogen atomic ratio within 2 percent of the ratio 3;

4;

a stress of 600 megapascals (MPa) to 1000 MPa; and

a hydrogen content of less than 5 atomic percent;

forming an etch mask over the silicon nitride layer;

removing the silicon nitride layer exposed by the etch mask;

subsequently removing the etch mask; and

forming a gate of the GaN FET over the cap layer, wherein the gate is in direct contact with the first surface of the cap layer at a center portion of the gate and partially overlaps the silicon nitride layer at end portions of the gate.

2. The method of claim 1, wherein the LPCVD process comprises:

placing the substrate in an LPCVD furnace;

heating the substrate to a temperature of 800°

C. to 820°

C. in the LPCVD furnace;

providing ammonia gas and dichlorosilane gas to a reaction chamber at a ratio of 4 to 6, and at a pressure of 150 millitorr to 250 millitorr; and

removing the substrate from the LPCVD furnace.

3. The method of claim 1, wherein removing the silicon nitride layer comprises an RIE process with fluorine radicals.

4. The method of claim 1, wherein the silicon nitride layer is less than 25 nanometers thick.

5. The method of claim 1, wherein the silicon nitride layer has an index of refraction of 2.0 to 2.1.

6. The method of claim 1, wherein the silicon nitride layer has a dielectric breakdown strength of greater than 12 megavolts per centimeter (MV/cm).

7. A method of forming a Gallium-Nitride Field Effect Transistor (GaN FET) device, comprising the steps:

forming a stack of gallium nitride and aluminum gallium nitride layers as a substrate;

forming a cap layer of gallium nitride on the stack;

forming a silicon nitride layer on a first surface of the cap layer using a low-pressure chemical vapor deposition (LPCVD) process by;

placing the substrate in an LPCVD furnace;

heating the substrate to a temperature of 800°

C. to 820°

C. in the LPCVD furnace;

providing ammonia gas and dichlorosilane gas to a reaction chamber at a ratio of 4 to 6, and at a pressure of 150 millitorr to 250 millitorr; and

removing the substrate from the LPCVD furnace;

forming an etch mask over the silicon nitride layer;

removing the silicon nitride layer exposed by the etch mask;

subsequently removing the etch mask; and

forming a gate structure of the GaN FET over the cap layer, wherein the gate structure is in direct contact with the first surface of the cap layer at a center portion of the gate structure and partially overlaps the silicon nitride layer at end portions of the gate structure.

8. The method of claim 7, wherein removing the silicon nitride layer comprises an RIE process with fluorine radicals.

9. The method of claim 7, wherein the silicon nitride layer is 10 nanometers to 20 nanometers thick.

10. The method of claim 7, wherein the silicon nitride layer has an index of refraction of 2.0 to 2.1.

11. The method of claim 7, wherein the silicon nitride layer has a dielectric breakdown strength of greater than 12 megavolts per centimeter (MV/cm).