Tungsten gates for non-planar transistors

• US 9,580,776 B2
• Filed: 09/21/2015
• Issued: 02/28/2017
• Est. Priority Date: 09/30/2011
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Intel Corporation
• Inventors: Pradhan, Sameer S., Bergstrom, Daniel B., Chun, Jin-Sung, Chiu, Julia
• Primary Examiner(s): SHOOK, DANIEL P
• Application Number:
  US14/860,341
• Publication Number:
  US 20160035725A1
• Time in Patent Office: 526 Days
• Field of Search: 257/412, 438/230
• US Class Current: 1/1
• CPC Class Codes: C22C 30/00 Alloys containing less than 50% by weight of each constituent
• CPC Class Codes: C23C 14/0635 Carbides
• CPC Class Codes: C23C 14/0652 Silicon nitride
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.

Claims

1. A device, comprising:

a substrate, wherein the substrate comprises a silicon fin;

a first dielectric layer on the substrate, wherein the first dielectric layer comprises silicon and oxygen;

a second dielectric layer on the first dielectric layer, wherein the second dielectric layer comprises hafnium and oxygen;

a pair of gate spacers on the substrate, wherein the gate spacers comprise a dielectric material;

an NMOS metal gate electrode above the second dielectric layer and between the pair of gate spacers, wherein the NMOS metal gate electrode comprises;

a first metal layer proximate the pair of gate spacers and above the second dielectric layer, wherein the first metal layer comprises titanium and nitrogen; and

a second metal layer on the first metal layer, wherein the second metal layer comprises tungsten;

a source region proximate to one of the pair of gate spacers, and a drain region proximate the other one of the pair of gate spacers, wherein the source region and the drain region comprise an n-type dopant;

a first contact coupled to the source region, wherein the first contact comprises a tungsten material above a first barrier layer; and

a second contact coupled to the drain region, wherein the second contact comprises a tungsten material above a second barrier layer.

2. The device of claim 1, wherein the NMOS metal gate electrode is non-planar.

3. The device of claim 1, wherein the NMOS work function material comprises between about 20 percent by weight to about 40 percent by weight aluminum, between about 30 weight percent to about 50 weight percent titanium, and between about 10 weight percent to about 30 weight percent carbon.

4. The device of claim 1, further including a capping dielectric structure disposed adjacent the NMOS metal gate electrode and between the pair of gate spacers.

5. The device of claim 1, wherein the second dielectric layer comprises a high k dielectric layer.

6. The device of claim 1, wherein the first metal layer comprises a barrier layer.

7. The device of claim 1, wherein the second metal layer comprises a fill layer.

8. The device of claim 1, wherein a material composition of a dielectric material directly adjacent the pair of spacers differs from the material composition of the pair of gate spacers.

9. An assembly, comprising:

a first transistor comprising;

a substrate, wherein the substrate comprises a silicon fin;

a first dielectric layer on the substrate, wherein the first dielectric layer comprises silicon and oxygen;

a second dielectric layer on the first dielectric layer, wherein the second dielectric layer comprises hafnium and oxygen;

a pair of gate spacers on the substrate, wherein the gate spacers comprise a dielectric material;

a NMOS metal gate electrode above the second dielectric material and between the pair of gate spacers, wherein the first NMOS metal gate electrode comprises;

a work function layer proximate the pair of gate spacers and above the second dielectric layer, wherein the work function layer comprises aluminum, titanium and carbon;

a barrier layer on the work function layer, wherein the barrier layer comprises titanium and nitrogen;

a source region proximate to one of the pair of gate spacers, and a drain region

proximate the other one of the pair of gate spacers, wherein the source region and the drain region comprise an n-type dopant;

a first contact coupled to the source region, wherein the first contact comprises a tungsten material above a first barrier layer;

a second contact coupled to the drain region, wherein the second contact comprises a tungsten material above a second barrier layer; and

a second transistor comprising;

a substrate, wherein the substrate comprises silicon fin;

a first dielectric layer on the substrate, wherein the first dielectric layer comprises silicon and oxygen;

a second dielectric layer on the first dielectric layer, wherein the second dielectric layer comprises hafnium and oxygen;

a pair of gate spacers on the substrate, wherein the gate spacers comprise a dielectric material;

a NMOS metal gate electrode above the second dielectric material and between the pair of gate spacers, wherein the NMOS metal gate electrode comprises;

a barrier layer on the high k dielectric material, wherein the barrier layer comprises titanium and nitrogen;

a tungsten-containing gate fill material on the titanium-containing barrier material;

a source region proximate to one of the pair of gate spacers, and a drain region proximate the other one of the pair of gate spacers, wherein the source region and the drain region comprise an n-type dopant;

a first contact coupled to the source region, wherein the first contact comprises a tungsten material above a first barrier layer; and

a second contact coupled to the drain region, wherein the second contact comprises a tungsten material above a second barrier layer.

10. The device of claim 9, wherein the assembly comprises a portion of an integrated circuit.