Tungsten gates for non-planar transistors
First Claim
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1. A device, comprising:
- a substrate, wherein the substrate comprises a silicon fin;
a first dielectric layer on the substrate, wherein the first dielectric layer comprises silicon and oxygen;
a second dielectric layer on the first dielectric layer, wherein the second dielectric layer comprises hafnium and oxygen;
a pair of gate spacers on the substrate, wherein the gate spacers comprise a dielectric material;
an NMOS metal gate electrode above the second dielectric layer and between the pair of gate spacers, wherein the NMOS metal gate electrode comprises;
a first metal layer proximate the pair of gate spacers and above the second dielectric layer, wherein the first metal layer comprises titanium and nitrogen; and
a second metal layer on the first metal layer, wherein the second metal layer comprises tungsten;
a source region proximate to one of the pair of gate spacers, and a drain region proximate the other one of the pair of gate spacers, wherein the source region and the drain region comprise an n-type dopant;
a first contact coupled to the source region, wherein the first contact comprises a tungsten material above a first barrier layer; and
a second contact coupled to the drain region, wherein the second contact comprises a tungsten material above a second barrier layer.
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Abstract
The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.
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Citations
10 Claims
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1. A device, comprising:
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a substrate, wherein the substrate comprises a silicon fin; a first dielectric layer on the substrate, wherein the first dielectric layer comprises silicon and oxygen; a second dielectric layer on the first dielectric layer, wherein the second dielectric layer comprises hafnium and oxygen; a pair of gate spacers on the substrate, wherein the gate spacers comprise a dielectric material; an NMOS metal gate electrode above the second dielectric layer and between the pair of gate spacers, wherein the NMOS metal gate electrode comprises; a first metal layer proximate the pair of gate spacers and above the second dielectric layer, wherein the first metal layer comprises titanium and nitrogen; and a second metal layer on the first metal layer, wherein the second metal layer comprises tungsten; a source region proximate to one of the pair of gate spacers, and a drain region proximate the other one of the pair of gate spacers, wherein the source region and the drain region comprise an n-type dopant; a first contact coupled to the source region, wherein the first contact comprises a tungsten material above a first barrier layer; and a second contact coupled to the drain region, wherein the second contact comprises a tungsten material above a second barrier layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An assembly, comprising:
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a first transistor comprising; a substrate, wherein the substrate comprises a silicon fin; a first dielectric layer on the substrate, wherein the first dielectric layer comprises silicon and oxygen; a second dielectric layer on the first dielectric layer, wherein the second dielectric layer comprises hafnium and oxygen; a pair of gate spacers on the substrate, wherein the gate spacers comprise a dielectric material; a NMOS metal gate electrode above the second dielectric material and between the pair of gate spacers, wherein the first NMOS metal gate electrode comprises; a work function layer proximate the pair of gate spacers and above the second dielectric layer, wherein the work function layer comprises aluminum, titanium and carbon; a barrier layer on the work function layer, wherein the barrier layer comprises titanium and nitrogen; a source region proximate to one of the pair of gate spacers, and a drain region proximate the other one of the pair of gate spacers, wherein the source region and the drain region comprise an n-type dopant; a first contact coupled to the source region, wherein the first contact comprises a tungsten material above a first barrier layer; a second contact coupled to the drain region, wherein the second contact comprises a tungsten material above a second barrier layer; and a second transistor comprising; a substrate, wherein the substrate comprises silicon fin; a first dielectric layer on the substrate, wherein the first dielectric layer comprises silicon and oxygen; a second dielectric layer on the first dielectric layer, wherein the second dielectric layer comprises hafnium and oxygen; a pair of gate spacers on the substrate, wherein the gate spacers comprise a dielectric material; a NMOS metal gate electrode above the second dielectric material and between the pair of gate spacers, wherein the NMOS metal gate electrode comprises; a barrier layer on the high k dielectric material, wherein the barrier layer comprises titanium and nitrogen; a tungsten-containing gate fill material on the titanium-containing barrier material; a source region proximate to one of the pair of gate spacers, and a drain region proximate the other one of the pair of gate spacers, wherein the source region and the drain region comprise an n-type dopant; a first contact coupled to the source region, wherein the first contact comprises a tungsten material above a first barrier layer; and a second contact coupled to the drain region, wherein the second contact comprises a tungsten material above a second barrier layer. - View Dependent Claims (10)
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Specification