Chip-on-wafer process control monitoring for chip-on-wafer-on-substrate packages

• US 9,581,638 B2
• Filed: 05/30/2013
• Issued: 02/28/2017
• Est. Priority Date: 03/13/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wu, Wei-Cheng, Hsu, Li-Han, Chiu, Sao-Ling, Hou, Shang-Yun, Jeng, Shin-Puu, Lin, Chen-Hua
• Primary Examiner(s): Tang, Minh N
• Assistant Examiner(s): FREDERIKSEN, DAVID B
• Application Number:
  US13/905,958
• Publication Number:
  US 20140266283A1
• Time in Patent Office: 1,370 Days
• Field of Search: 324/756.03, 324/762.05, 324/750.3, 324/500, 324/512, 324/522, 324/527, 324/73.1
• US Class Current: 1/1
• CPC Class Codes: G01R 1/07314 the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support on an elastic support, e.g. a film, G01R1/0735
• CPC Class Codes: G01R 31/265 Contactless testing of circuits, also in wafer-form G01R31/302
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2224/16055 being circular or elliptic
• CPC Class Codes: H01L 2224/16113 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/1713 Square or rectangular array
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence

Abstract

An embodiment method includes providing a standardized testing structure design for a chip-on-wafer (CoW) structure, wherein the standardized testing structure design comprises placing a testing structure in a pre-selected area a top die in the CoW structure, and electrically testing a plurality of microbumps in the CoW structure by applying a universal testing probe card to the testing structure.

Claims

1. A method for testing a chip-on-wafer (CoW) structure comprising:

providing a standardized testing structure design for a CoW structure, wherein the standardized testing structure design comprises placing a testing structure in a pre-selected area within a top die in the CoW structure, wherein the top die comprises functional circuits independent from and formed on a same substrate as the testing structure, wherein the testing structure has a same circuit layout as an additional testing structure within an additional top die of an additional CoW structure, and wherein the additional top die comprises additional functional circuits having a different circuit layout than the functional circuits of the top die; and

electrically testing a plurality of microbumps between the top die and another die in the CoW structure by applying a universal testing probe card to transmit an electrical signal through the testing structure, wherein a same electrical signal is sent through the additional testing structure as the electrical signal when electrically testing the additional CoW structure.

2. The method of claim 1, wherein:

providing the standardized testing structure design further includes placing a probing pad on a peripheral region of a bottom die of the CoW structure and electrically connected to the testing structure; and

electrically testing the plurality of microbumps comprises applying the universal testing probe card to the testing structure through the probing pad.

3. The method of claim 1, wherein placing the testing structure in the pre-selected area of the CoW structure comprises placing the testing structure in a center region of the top die.

4. The method of claim 1, wherein placing the testing structure in the pre-selected area of the CoW structure comprises placing the testing structure in a corner region of the top die.

5. The method of claim 1, further comprising, after electrically testing the plurality of microbumps, physically examining a sample of the plurality of microbumps using an x-ray.

6. The method of claim 1, wherein providing the standardized testing structure design further comprises including a daisy chain in the testing structure.

7. The method of claim 1, wherein providing the standardized testing structure design further comprises including a kelvin structure in the testing structure.

8. The method of claim 1, wherein providing the standardized testing structure design further comprises configuring the testing structure in an L-shape.

9. The method of claim 1, wherein the testing structure comprises a plurality of electrically interconnected conductive lines electrically connected to microbumps bonding the top die to the another die, wherein the additional testing structure further comprises an additional plurality of electrically interconnected conductive lines, and wherein a layout of the plurality of electrically interconnected conductive lines is the same as a layout of the additional plurality of electrically interconnected conductive lines.

10. A method for testing a chip-on-wafer (CoW) structure comprising:

designing, by a processor, a plurality of standardized testing structures for placement in pre-selected regions of a CoW structure;

forming a plurality of CoW structures, wherein each of the plurality of CoW structures include;

a top die comprising;

the plurality of standardized testing structures, wherein the plurality of standardized testing structures comprise a same circuit layout in different ones of the plurality of CoW structures; and

additional functional circuits independent from the plurality of standardized testing structures, wherein the additional functional circuits comprise different circuit layouts in the different ones of the plurality of CoW structures; and

a bottom die bonded to the top die by microbump connections, wherein the plurality of standardized testing structures are electrically connected to a plurality of probing pads disposed in peripheral regions of the bottom die; and

electrically testing the microbump connections of the plurality of CoW structures by transmitting a same electrical signal through each of the plurality of CoW structures.

11. The method of claim 10, wherein electrically testing the microbump connections of the plurality of CoW structures comprises applying a universal testing probe card to the plurality of probing pads in each of the plurality of CoW structures, wherein the universal testing probe card is configured to test a variety of different CoW structures having different chip layouts.

12. The method of claim 10, wherein the pre-selected regions of the CoW structure are corner regions of a top die in the CoW structure.

13. The method of claim 10, wherein the pre-selected regions of the CoW structure are center regions of a top die in the CoW structure.

14. A chip-on-wafer (CoW) testing mechanism comprising:

a standardized testing structure configured to be placed in a pre-selected region within a top die of a CoW structure, wherein the standardized testing structure comprises microbumps and a plurality of electrically interconnected conductive lines in the top die and electrically connected to the microbumps;

wherein the top die further comprises functional circuits independent from and formed on a same substrate as the standardized testing structure, wherein additional standardized testing structures having a same circuit layout as the standardized testing structure are configured to be placed in a variety of top dies of a variety of CoW structures, wherein the variety of top dies each comprise a different functional circuit layout, wherein each of the additional standardized testing structure comprises;

additional microbumps; and

an additional plurality of electrically interconnected conductive lines in a respective one of the variety of top dies and electrically connected to the additional microbumps, and wherein the plurality of electrically interconnected conductive lines has a same layout as the additional plurality of electrically interconnected conductive lines; and

a probing pad configured to be placed in a peripheral region of a bottom die of the CoW structure and electronically connected to the standardized testing structure.

15. The CoW testing mechanism of claim 14, wherein the standardized testing structure includes a first daisy chain at a first location in the top die, wherein the additional standardized testing structure includes a second daisy chain having a same layout as the first daisy chain, and wherein the second daisy chain is disposed in a same relative location in each of the variety of top dies as the first location.

16. The CoW testing mechanism of claim 14, wherein the standardized testing structure includes a first kelvin structure at a second location in the top die, wherein the additional standardized testing structure includes a second kelvin structure having a same layout as the first kelvin structure, and wherein the second kelvin structure is disposed in a same relative location in each of the variety of top dies as the second location.

17. The CoW testing mechanism of claim 14, wherein the standardized testing structure has an L-shape.

18. The CoW testing mechanism of claim 14, wherein the top die is an active device die and the bottom die is an interposer.

19. The CoW testing mechanism of claim 14, wherein the bottom die comprises contact pads contacting the microbumps, wherein the probing pad is located on a same surface of the bottom die as the contact pads, and wherein the probing pad is exposed when the top die is bonded to the bottom die.