Dual mode clock using a common resonator and associated method of use
First Claim
1. An integrated circuit providing a dual mode clock output signal, the integrated circuit comprising:
- a resonator;
a first clock circuit having a first oscillator circuit coupled to the resonator, the first clock circuit for generating a first clock signal having a first frequency in response to the resonator;
a second clock circuit having a second oscillator circuit coupled to the resonator and a programmable frequency divider, the second clock circuit for generating a second clock signal having a second frequency in response to the resonator, wherein the second frequency of the second clock signal is determined by the programmable frequency divider; and
a clock mode control circuit coupled to the first clock circuit and the second clock circuit, the clock mode control circuit for gradually switching the resonator between the first oscillator circuit and the second oscillator circuit to provide a dual mode clock output signal.
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Accused Products
Abstract
An integrated circuit comprising, a resonator, a first clock circuit for generating a first clock signal having a first frequency in response to the resonator, a second clock circuit for generating a second clock signal having a second frequency in response to the resonator, wherein the second frequency of the second clock signal is determined by the programmable frequency divider and a clock mode control circuit coupled to the first clock circuit and the second clock circuit, the clock mode control circuit for gradually switching the resonator between the first oscillator circuit and the second oscillator circuit of the integrated circuit, using a shift register based state machine and utilizing the inertia of the resonator to smoothly transition between the two oscillators, to provide a dual mode clock output signal.
119 Citations
20 Claims
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1. An integrated circuit providing a dual mode clock output signal, the integrated circuit comprising:
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a resonator; a first clock circuit having a first oscillator circuit coupled to the resonator, the first clock circuit for generating a first clock signal having a first frequency in response to the resonator; a second clock circuit having a second oscillator circuit coupled to the resonator and a programmable frequency divider, the second clock circuit for generating a second clock signal having a second frequency in response to the resonator, wherein the second frequency of the second clock signal is determined by the programmable frequency divider; and a clock mode control circuit coupled to the first clock circuit and the second clock circuit, the clock mode control circuit for gradually switching the resonator between the first oscillator circuit and the second oscillator circuit to provide a dual mode clock output signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. An integrated circuit providing a dual mode clock output signal, the integrated circuit comprising:
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a resonator having a resonant frequency; a high performance clock circuit having an inverting amplifier based oscillator circuit, the high performance clock circuit for generating a first clock signal having a first frequency in response to the resonant frequency of the resonator; a low power clock circuit having a current starved amplifier based oscillator circuit and a programmable frequency divider, the low power clock circuit for generating a second clock signal having a second frequency in response to the resonator, wherein the second frequency of the second clock signal is different than the first frequency of the first clock signal; and a clock mode control circuit coupled to the high performance clock circuit and the low power clock circuit, the clock mode control circuit for gradually switching the resonator between the inverting amplifier based oscillator circuit and the current starved amplifier based oscillator circuit to provide a dual mode clock output signal.
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15. A method of generating a dual mode clock output signal, the method comprising:
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coupling a resonator to a first oscillator circuit of a first clock circuit, the first clock circuit for generating a first clock signal having a first frequency in response to the resonator; coupling the resonator to a second oscillator circuit of a second clock circuit, the second clock circuit for generating a second clock signal having a second frequency in response to the resonator, wherein the second frequency of the second clock signal is determined by a programmable frequency divider of the second clock circuit; coupling a clock mode control circuit to the first clock circuit and the second clock circuit; and operating the clock mode control circuit to gradually switch the resonator between the first oscillator circuit and the second oscillator circuit to generate a dual mode clock output signal. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification