Automated processor generation system and method for designing a configurable processor

• US 9,582,278 B2
• Filed: 10/09/2008
• Issued: 02/28/2017
• Est. Priority Date: 02/17/2000
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Wang, Albert Ren-Rui, Ruddell, Richard, Goodwin, David William, Killian, Earl A., Bhattacharyya, Nupur, Medina, Marines Puig, Lichtenstein, Walter David, Konas, Pavlos, Srinivasan, Rangarajan, Songer, Christopher Mark, Parameswar, Akilesh, Maydan, Dror E., Gonzalez, Ricardo E.
• Primary Examiner(s): DO, THUAN V
• Application Number:
  US12/248,883
• Publication Number:
  US 20090172630A1
• Time in Patent Office: 3,064 Days
• Field of Search: 716/136
• US Class Current: 1/1
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants

Abstract

A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Claims

1. A computer-implemented system for designing a configurable processor, the system comprising:

hardware generation means for, based on a user-defined specification, generating a description of a hardware implementation of the processor;

software generation means for, based on the user-defined specification, generating software development tools specific to the hardware implementation; and

document generation means for generating documentation of an instruction set of the processor whose hardware implementation description and software development tools are generated by the hardware generation means and software means, respectively, based on the user-defined specification.

2. The system of claim 1, wherein the document generation means includes means for using reference semantics of instructions defined in the user-defined specification to generate the processor instruction set documentation.

3. The system of claim 1, wherein:

the user-defined specification contains reference semantics of an instruction defined therein and a user-defined specification of at least one of a synopsis and a text description for the user-defined instruction; and

the document generation means includes means for using the at least one of the synopsis and the text description to generate documentation of the processor instruction set.

4. The system of claim 1, wherein the user-defined specification includes a statement specifying scheduling information of instructions used in the software development tools, and wherein the hardware generation means includes means for, based on the statement in the user-defined specification, determining whether and how to generate a description of at least one of pipeline logic, pipeline stalling logic and instruction rescheduling logic.

5. The system of claim 4, wherein the scheduling information includes a statement that an operand of an instruction enters a pipeline of the processor at a given stage.

6. The system of claim 4, wherein the scheduling information includes a statement that an operation of an instruction exits a pipeline of the processor at a given stage.

7. The system of claim 4, wherein:

the software generated by the software generation means includes a compiler which uses instructions described in the user-defined specification; and

the compiler uses the scheduling information during instruction scheduling to schedule the instructions described in the user-defined specification.

8. The system of claim 1, wherein the user-defined specification includes a description of an instruction which requires a plurality of processor cycles to be processed.

9. The system of claim 8, wherein:

the user-defined specification includes a description of an instruction'"'"'s semantics which is independent of a target pipeline of the processor; and

the hardware generation means includes means for generating as part of the processor hardware implementation a pipeline based on a pipeline description separate from the instruction semantics.

10. The system of claim 1, wherein the generated documentation comprises a textual instruction set reference manual.

11. A computer-implemented method for designing a configurable processor, the method comprising:

generating, based on a user-defined specification a description of a hardware implementation of the processor;

generating, based on the user-defined specification, software development tools specific to the hardware implementation; and

generating documentation of an instruction set of the processor having the generated hardware implementation description and software development tools, based on the user-defined specification.

12. The method of claim 11, wherein the documentation generating step includes using reference semantics of instructions defined in the user-defined specification to generate the processor instruction set documentation.

13. The method of claim 11, wherein:

the user-defined specification contains reference semantics of an instruction defined therein and a user-defined specification of at least one of a synopsis and a text description for the user-defined instruction; and

the documentation generation step includes using the at least one of the synopsis and the text description to generate documentation of the processor instruction set.

14. The method of claim 11, wherein the user-defined specification includes a statement specifying scheduling information of instructions used in the software development tools, and wherein the hardware generation step includes, based on the statement in the user-defined specification, determining whether and how to generate a description of at least one of pipeline logic, pipeline stalling logic and instruction rescheduling logic.

15. The method of claim 14, wherein the scheduling information includes a statement that an operand of an instruction enters a pipeline of the processor at a given stage.

16. The method of claim 14, wherein the scheduling information includes a statement that an operation of an instruction exits a pipeline of the processor at a given stage.

17. The method of claim 14, wherein:

the software generated by the software generation step includes a compiler which uses instructions described in the user-defined specification; and

the compiler uses the scheduling information during instruction scheduling to schedule the instructions described in the user-defined specification.

18. The method of claim 11, wherein the user-defined specification includes a description of an instruction which requires a plurality of processor cycles to be processed.

19. The method of claim 18, wherein:

the user-defined specification includes a description of an instruction'"'"'s semantics which is independent of a target pipeline of the processor; and

the hardware generation step includes generating as part of the processor hardware implementation a pipeline based on a pipeline description separate from the instruction semantics.

20. The method of claim 11, wherein the step of generating documentation includes generating a textual instruction set reference manual.