Computer systems and methods with resource transfer hint instruction

• US 9,582,320 B2
• Filed: 03/14/2013
• Issued: 02/28/2017
• Est. Priority Date: 03/14/2013
• Status: Expired due to Fees

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Inventors: Holt, James C., Kahne, Brian C., Moyer, William C.
• Primary Examiner(s): Puente, Emerson
• Assistant Examiner(s): Chen, Zhi
• Application Number:
  US13/826,117
• Publication Number:
  US 20140282561A1
• Time in Patent Office: 1,447 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 2209/486 Scheduler internals
• CPC Class Codes: G06F 9/462 with multiple register sets
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues

Abstract

A processing system includes a processor configured to execute a plurality of instructions corresponding to a task, wherein the plurality of instructions comprises a resource transfer instruction to indicate a transfer of processing operations of the task from the processor to a different resource and a hint instruction which precedes the resource transfer instruction by a set of instructions within the plurality of instructions. A processor task scheduler is configured to schedule tasks to the processor, wherein, in response to execution of the hint instruction of the task, the processor task scheduler finalizes selection of a next task and loads a context of the selected next task into a background register file. The loading occurs concurrently with execution of the set of instructions between the hint instruction and resource transfer instruction, and, after loading is completed, the processor switches to the selected task in response to the resource transfer instruction.

Claims

1. A processing system, comprising:

a processor configured to execute a plurality of instructions corresponding to a task, wherein the plurality of instructions comprises a resource transfer instruction to indicate a transfer of processing operations of the task from the processor to a different resource and a hint instruction which precedes the resource transfer instruction by a set of instructions within the plurality of instructions; and

a processor task scheduler, coupled to the processor, configured to schedule tasks to the processor, wherein, in response to execution of the hint instruction of the task, the processor task scheduler finalizes selection of a next task to utilize the processor and loads a context of the selected next task into a background register file of the processor, wherein;

the loading of the context of the selected next task occurs concurrently with execution of the set of instructions between the hint instruction and resource transfer instruction of the task, and

after the loading of the context of the selected next task is completed, the processor switches to the selected task in response to the resource transfer instruction; and

wherein a time required to execute the set of instructions after execution of the hint instruction is predicted to be at least as long as a time required to load the context of the selected new task into the background register file.

2. The processing system of claim 1, wherein the processor task scheduler is configured to provide a completion indicator to the processor when the loading of the selected next task is completed.

3. The processing system of claim 1, wherein the processor uses the background register file as an active register file when processing instructions of the selected next task.

4. The processing system of claim 1, wherein the processor, upon switching to the selected task, transfers information from the background register file to an active register file of the processor.

5. The processing system of claim 1, wherein the processor, in response to execution of the hint instruction, provides a hint indicator to the processor task scheduler, wherein the processor task scheduler finalizes the selection of the next task to utilize the processor in response to the hint indicator.

6. The processing system of claim 1, wherein the different resource is characterized as a hardware accelerator.

7. The processing system of claim 1, wherein the processor task scheduler is configured to evaluate priorities of schedulable tasks, wherein the finalizing the selection of a next task to utilize the processor comprises selecting one of the schedulable tasks based on the priorities.

8. The processing system of claim 1, wherein the processor task scheduler is configured to evaluate priorities of schedulable tasks and make initial selections of a next task during the evaluating, wherein the finalizing the selection of the next task comprises using the most recently made initial selection of the next task.

9. A method comprising:

executing, by a processor, instructions of a corresponding task, wherein the instructions comprise;

a resource transfer instruction to indicate a transfer of processing operations of the task from the processor to a different resource; and

a hint instruction which precedes the resource transfer instruction by a set of instructions;

in response to executing the hint instruction, providing a hint indicator to a task scheduler;

in response to the hint indicator, finalizing, by the task scheduler, a selection of a next task to be scheduled;

loading a context of the selected next task into a background register file of the processor, wherein the loading of the context of the selected next task is performed by the task scheduler while the processor executes the set of instructions between the hint instruction and the resource transfer instruction; and

after the loading the context of the selected next task, switching, by the processor, to the selected next task in response to the resource transfer instruction; and

wherein a time required to execute the set of instructions after execution of the hint instruction is predicted to be at least as long as a time required to load the context of the selected new task into the background register file.

10. The method of claim 9, further comprising:

providing, by the task scheduler, a completion indicator to the processor when the loading of the selected next task is completed, wherein the switching, by the processor, to the selected task is performed in response to the resource transfer instruction and the completion indicator.

11. The method of claim 9, further comprising:

executing, by the processor, instructions of the selected next task, wherein the processor uses the background register file as an active register file when executing the instructions of the selected next task.

12. The method of claim 9, further comprising:

transferring information from the background register file to an active register file of the processor; and

after the transferring the information, executing, by the processor, instructions of the selected next task, wherein the processor uses the active register file when executing the instructions of the selected next task.

13. The method of claim 9, wherein the different resource is characterized as a hardware accelerator.

14. The method of claim 9, wherein the finalizing the selection of a next task to utilize the processor comprises selecting one of a plurality of schedulable tasks based on priorities of the schedulable tasks.

15. The method of claim 9, wherein finalizing the selection of a next task to utilize the processor comprises using a most recently selected next task of a plurality of schedulable tasks which was selected prior to receiving the hint indicator.

16. A method of inserting a hint instruction into a plurality of instructions executable by a processor corresponding to a task, comprising:

identifying a resource transfer instruction within the plurality of instructions, wherein execution of the resource transfer instructions causes a transfer from a current resource to a new resource;

identifying a window of instructions preceding the resource transfer instruction whose predicted execution time is within an amount of time required to perform a load of task context information for a context switch; and

combining a hint instruction with the window of instructions, wherein the hint instruction, upon execution by the processor, provides an indication that the resource transfer instruction will be executed subsequent to the hint instruction.

17. The method of claim 16, wherein instructions between the hint instruction and the resource transfer instruction is characterized as a basic block of instructions.

18. The method of claim 16, wherein combining the hint instruction with the window of instructions comprises inserting the hint instruction as a first instruction to be executed in the window of instructions.