System and method for DDR memory timing acquisition and tracking

• US 9,582,356 B1
• Filed: 10/24/2014
• Issued: 02/28/2017
• Est. Priority Date: 11/01/2013
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Liu, Peter Tze-Hwa, Mishra, Saswat
• Primary Examiner(s): LAMARRE, GUY J
• Application Number:
  US14/522,695
• Time in Patent Office: 858 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 13/4234 being a memory bus
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

Systems, methods, and other embodiments associated with providing real time closed loop control of memory access are described. According to one embodiment, a method includes accessing a memory of a computing device during real time operation of the computing device and detecting bit errors associated with the accessing of the memory. The method also includes generating a performance metric based on, at least in part, the detected bit errors during the real time operation of the computing device. The method further includes adjusting a setting of at least one timing element, of a plurality of timing elements of a physical layer of the computing device, based on the performance metric during the real time operation of the computing device to maintain a determined memory access performance.

Claims

1. An apparatus comprising:

memory configured to be accessed by having data written thereto and read therefrom;

memory control logic configured to control memory access of the memory via a plurality of signal lines;

physical layer logic configured to provide a tunable signal interface for the plurality of signal lines between the memory control logic and the memory; and

performance monitor logic configured to provide closed loop control, to maintain a determined apparatus performance associated with the memory access, by;

(i) detecting bit errors associated with the memory access during real time operation of the apparatus,

(ii) generating a performance metric based on, at least in part, the detected bit errors during the real time operation of the apparatus, and

(iii) tuning a signal parameter of at least one signal associated with at least one signal line of the plurality of signal lines via the physical layer logic based on, at least in part, the performance metric during the real time operation of the apparatus.

2. The apparatus of claim 1, wherein the memory comprises a double data rate memory.

3. The apparatus of claim 1, wherein the performance monitor logic is configured to correct the detected bit errors via error control coding techniques during the real time operation of the apparatus.

4. The apparatus of claim 1, wherein the plurality of signal lines comprise clock signal lines, address signal lines, command signal lines, and control signal lines.

5. The apparatus of claim 1, wherein the signal parameter comprises at least one of a time delay and a timing window position.

6. The apparatus of claim 1, wherein the plurality of signal lines are configured to communicate analog signals, and wherein a frequency of at least one of the analog signals is greater than or equal to 800 MHz.

7. The apparatus of claim 1, wherein the plurality of signal lines are configured to communicate analog signals, and wherein a frequency of at least one of the analog signals is greater than or equal to 1600 MHz.

8. The apparatus of claim 1, wherein a portion of the memory is configured based on error control coding techniques performed by the performance monitor logic.

9. The apparatus of claim 1, wherein the determined apparatus performance is a bit error rate associated with the memory access of the memory.

10. The apparatus of claim 1, wherein the apparatus is a system-on-chip device further comprising:

central processing logic, operably connected to the memory control logic, configured to provide commands to the memory control logic via a first communication bus; and

direct memory access logic, operably connected to the memory control logic and the central processing logic, configured to access the memory via a second communication bus.

11. A computer-implemented method performed by a computing device where the computing device includes at least a processor for executing instructions from a memory, the method comprising:

accessing a memory of the computing device during real time operation of the computing device via at least the processor;

detecting bit errors associated with the accessing of the memory during the real time operation of the computing device via at least the processor;

generating a performance metric based on, at least in part, the detected bit errors during the real time operation of the computing device via at least the processor; and

adjusting a setting of at least one timing element, of a plurality of timing elements of a physical layer of the computing device, based on the performance metric during the real time operation of the computing device, via at least the processor, to maintain a determined memory access performance.

12. The computer-implemented method of claim 11, further comprising initializing settings of the plurality of timing elements, via at least the processor, to initially achieve the determined memory access performance.

13. The computer-implemented method of claim 11, wherein the determined memory access performance is a bit error rate.

14. The computer-implemented method of claim 11, further comprising correcting the detected bit errors via error control coding techniques during the real time operation of the computing device via at least the processor.

15. The computer-implemented method of claim 11, wherein at least a portion of the accessing of the memory during the real time operation of the computing device is based on error control coding techniques.

16. An integrated circuit device, comprising:

central processing logic;

direct memory access logic operably connected to the central processing logic;

double data rate memory; and

memory control logic, operably connected to the central processing logic and the direct memory access logic, configured to provide continuous real time closed loop control to maintain a determined memory access performance of the double data rate memory during real time operation of the integrated circuit device,

wherein the central processing logic, the direct memory access logic, and the memory control logic are configured as at least one integrated circuit on a chip.

17. The integrated circuit device of claim 16, further comprising a physical layer logic configured to provide a plurality of signal lines to the double data rate memory for controlling memory access of the double data rate memory under the control of the memory control logic, wherein the physical layer logic is configured as an integrated circuit on a chip.

18. The integrated circuit device of claim 17, wherein the physical layer logic comprises a plurality of tapped delay lines and registers, associated with the plurality of signal lines, configured to be adjusted under the control of the memory control logic to tune time delays and timing window positions associated with analog signals associated with the plurality of signal lines as part of the closed loop control.

19. The integrated circuit device of claim 16, further comprising error control coding logic configured to correct bit errors associated with accessing the double data rate memory, wherein the error control coding logic is configured as an integrated circuit on a chip.

20. The integrated circuit device of claim 18, wherein at least one frequency of at least one signal of the analog signals is greater than or equal to 800 Mhz.