Write mapping to mitigate hard errors via soft-decision decoding

• US 9,582,359 B2
• Filed: 12/09/2015
• Issued: 02/28/2017
• Est. Priority Date: 06/23/2014
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Alhussien, AbdelHakim S., Haratsch, Erich F., Cohen, Earl T., Wu, Yunxiang
• Primary Examiner(s): Blair, April Y.
• Assistant Examiner(s): GANDHI, DIPAKKUMAR B
• Application Number:
  US14/963,723
• Publication Number:
  US 20160098317A1
• Time in Patent Office: 447 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/0727 in a storage system, e.g. in a DASD or network based storage system drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/152 Bose-Chaudhuri-Hocquenghem [BCH] codes
• CPC Class Codes: H03M 13/256 with trellis coding, e.g. with convolutional codes and TCM
• CPC Class Codes: H03M 13/2906 using block codes H03M13/2957 takes precedence
• CPC Class Codes: H03M 13/45 Soft decoding, i.e. using symbol reliability information H03M13/41 takes precedence
• CPC Class Codes: H03M 13/458 by updating bit probabilities or hard decisions in an iterative fashion for convergence to a final decoding result

Abstract

An apparatus having mapping and interface circuits. The mapping circuit (i) generates a coded item by mapping write unit bits using a modulation or recursion of past-seen bits, and (ii) calculates a particular state to program into a nonvolatile memory cell. The interface circuit programs the cell at the particular state. Two normal cell states are treated as at least four refined states. The particular state is one of the refined states. A mapping to the refined states mitigates programming write misplacement that shifts an analog voltage of the cell from the particular state to an erroneous state. The erroneous state corresponds to a readily observable illegal or atypical write sequence, and results in a modified soft decision from that calculated based on the normal states only. A voltage swing between the particular state and the erroneous state is less than between the normal states.

Claims

1. A method for mitigating hard errors, comprising the steps of:

creating a plurality of inter-bit dependencies between a current bit in a sequence of data bits and a plurality of neighboring bits in the sequence of data bits to generate a plurality of mapped bits;

writing the plurality of mapped bits among at least two cells of a plurality of memory cells in a memory with at least two of the plurality of mapped bits stored in each of the plurality of memory cells;

generating a plurality of log-likelihood ratio values in response to reading the plurality of mapped bits from the memory, wherein each of the log-likelihood ratio values is based on two or more of the mapped bits and is representative of the plurality of inter-bit dependencies, and the plurality of inter-bit dependencies mitigate a hard error due to one of the at least two cells being stuck in a fixed state; and

decoding the plurality of mapped bits based on the plurality of log-likelihood ratio values to recover the current bit.

2. The method according to claim 1, wherein the plurality of inter-bit dependencies result in a less than saturated value in the plurality of log-likelihood ratio values due to a single-bit write error among the plurality of mapped bits.

3. The method according to claim 1, wherein the plurality of inter-bit dependencies are created using a modulation of the plurality of neighboring bits.

4. The method according to claim 1, further comprising the step of:

encoding data to generate the current bit and the plurality of neighboring bits.

5. The method according to claim 1, wherein the plurality of inter-bit dependencies are created using a recursion of the plurality of neighboring bits.

6. The method according to claim 1, wherein the plurality of inter-bit dependencies increase a Euclidean-space distance between likely bit sequences to greater than a single-bit error.

7. The method according to claim 1, wherein the plurality of inter-bit dependencies adjusts a written state voltage of the mapped bits in the memory in response to a most recent one of the plurality of neighboring bits being a logical one bit.

8. The method according to claim 1, wherein the steps are performed in a solid-state drive controller.

9. An apparatus comprising:

an interface configured to process a plurality of read/write operations to/from a memory; and

a control circuit configured to create a plurality of inter-bit dependencies between a current bit in a sequence of data bits and a plurality of neighboring bits in the sequence of data bits to generate a plurality of mapped bits, write the plurality of mapped bits among at least two cells of a plurality of memory cells in the memory with at least two of the plurality of mapped bits stored in each of the plurality of memory cells, generate a plurality of log-likelihood ratio values in response to reading the plurality of mapped bits from the memory, and decode the plurality of mapped bits based on the plurality of log-likelihood ratio values to recover the current bit, wherein each of the log-likelihood ratio values is based on two or more of the mapped bits and is representative of the plurality of inter-bit dependencies, and the plurality of inter-bit dependencies mitigate a hard error due to one of the at least two cells being stuck in a fixed state.

10. The apparatus according to claim 9, wherein the plurality of inter-bit dependencies result in a less than saturated value in the plurality of log-likelihood ratio values due to a single-bit write error among the plurality of mapped bits.

11. The apparatus according to claim 9, wherein the plurality of inter-bit dependencies are created using a modulation of the plurality of neighboring bits.

12. The apparatus according to claim 9, wherein the control circuit is further configured to encode data to generate the current bit and the plurality of neighboring bits.

13. The apparatus according to claim 9, wherein the plurality of inter-bit dependencies are created using a recursion of the plurality of neighboring bits.

14. The apparatus according to claim 9, wherein the plurality of inter-bit dependencies increase a Euclidean-space distance between likely bit sequences to greater than a single-bit error.

15. The apparatus according to claim 9, wherein the plurality of inter-bit dependencies adjusts a written state voltage of the mapped bits in the memory in response to a most recent one of the plurality of neighboring bits being a logical one bit.

16. The apparatus according to claim 9, wherein the memory and the control circuit are part of a solid-state drive.

17. An apparatus comprising:

a memory configured to store data; and

a controller configured to create a plurality of inter-bit dependencies between a current bit in a sequence of data bits and a plurality of neighboring bits in the sequence of data bits to generate a plurality of mapped bits, write the plurality of mapped bits among at least two cells of a plurality of memory cells in the memory with at least two of the plurality of mapped bits stored in each of the plurality of memory cells, generate a plurality of log-likelihood ratio values in response to reading the plurality of mapped bits from the memory, and decode the plurality of mapped bits based on the plurality of log-likelihood ratio values to recover the current bit, wherein each of the log-likelihood ratio values is based on two or more of the mapped bits and is representative of the plurality of inter-bit dependencies, and the plurality of inter-bit dependencies mitigate a hard error due to one of the at least two cells being stuck in a fixed state.

18. The apparatus according to claim 17, wherein the plurality of inter-bit dependencies result in a less than saturated value in the plurality of log-likelihood ratio values due to a single-bit write error among the plurality of mapped bits.

19. The apparatus according to claim 17, wherein the plurality of inter-bit dependencies increase a Euclidean-space distance between likely bit sequences to greater than a single-bit error.

20. The apparatus according to claim 17, wherein the memory and the controller are part of a solid-state drive.