Setting a default read signal based on error correction

• US 9,582,362 B2
• Filed: 12/21/2015
• Issued: 02/28/2017
• Est. Priority Date: 12/06/2012
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ratnam, Sampath K., Yanamanamanda, Satish K.
• Primary Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US14/977,088
• Publication Number:
  US 20160110257A1
• Time in Patent Office: 435 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50004 of threshold voltage
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

The present disclosure includes apparatuses and methods related to setting a default read signal based on error correction. A number of methods can include reading a page of data from a group of memory cells with a first discrete read signal and error correcting at least one codeword of the page of data as read with the first discrete read signal. Methods can include reading a page of data from the group of memory cells with a second discrete read signal different than the first discrete read signal and error correcting at least one codeword of the page of data as read with the second discrete read signal. One of the first and the second discrete read signals can be set as a default read signal based at least in part on the respective error corrections.

Claims

1. A method, comprising:

reading data from a group of memory cells with a plurality of discrete read signals;

counting a number of errors corrected for the data read with each of the plurality of discrete read signals;

comparing the number of errors corrected for each of the plurality of discrete read signals; and

setting one of the plurality of discrete read signals as a default read signal based, at least in part, on the comparison.

2. The method of claim 1, wherein setting one of the plurality of discrete read signals as the default read signal based, at least in part, on the comparison comprises setting the one of the plurality of discrete read signals that results in a fewest number of errors as the default read signal.

3. The method of claim 1, wherein reading the data comprises reading a particular type of page of data from the group of memory cells, wherein the particular type of page of data is selected from the group including a lower page of data, a middle page of data, and an upper page of data.

4. The method of claim 3, wherein comparing the number of errors comprises comparing the number of errors for the particular type of page of data;

and

wherein setting one of the plurality of discrete read signals as the default read signal based at least in part on the comparison comprises setting the one of the plurality of discrete read signals that results in a fewest number of errors for the particular type of page of data as the default read signal for the particular type of page of data.

5. The method of claim 1, wherein reading the data with the plurality of discrete read signals comprises reading the data with the plurality of read signals each having a different magnitude.

6. The method of claim 1, wherein the method includes error correcting a respective page of data read from the group of memory cells with each of the plurality of discrete read signals.

7. The method of claim 6, wherein counting the number of errors corrected comprises counting the number of errors corrected during error correction after each reading of the group of memory cells with each of the plurality of discrete read signals.

8. The method of claim 1, wherein counting the number of errors corrected for the data read with each of the plurality of discrete read signals comprises counting a number codewords that have been error corrected.

9. The method of claim 1, wherein reading the data comprises reading the data with the plurality of discrete read signals as a test operation during idle time of a memory device.

10. The method of claim 1, wherein counting the number of errors corrected comprises counting the number of errors corrected for a particular die;

wherein comparing the number of errors comprises comparing the number of errors for the particular die; and

wherein setting one of the plurality of discrete read signals as the default read signal based at least in part on the comparison comprises setting the one of the plurality of discrete read signals that results in a fewest number of errors for the particular die as the default read signal for the particular die.

11. The method of claim 1, wherein counting the number of errors corrected for the data read with each of the plurality of discrete read signals comprises counting the number of errors corrected for the data read with each of the plurality of discrete read signals that do not return an uncorrectable error.

12. A method, comprising:

reading a page of user data from a group of memory cells with a first discrete read signal as part of a test operation of a memory apparatus;

counting a number of errors corrected for the data as read with the first discrete read signal;

reading the page of user data from the group of memory cells with a second discrete read signal as part of the test operation of the memory apparatus;

counting a number of errors corrected for the data as read with the second discrete read signal;

comparing the number of errors corrected for each of the first discrete read signal and the second discrete read signal; and

setting, during idle time of the memory apparatus, one of the first discrete read signal and the second discrete signal as a default read signal based, at least in part, on the comparison.

13. The method of claim 12, wherein counting the number of errors corrected for the data as read with the first discrete read signal and counting the number of errors corrected for the data as read with the second discrete read signal comprises counting the number of errors corrected for the data as read with the first discrete read signal and counting the number of errors corrected for the data as read with the second discrete read signal that do not return an uncorrectable error.

14. The method of claim 12, wherein the first discrete read signal and the second discrete read signal have different magnitudes.

15. An apparatus, comprising:

a memory array; and

a controller coupled to the memory array, and configured to;

read data from a group of memory cells with a plurality of discrete read signals;

count a number of errors corrected for the data read with each of the plurality of discrete read signals that do not return an uncorrectable error;

comparing the number of errors corrected for each of the plurality of discrete read signals; and

set one of the plurality of discrete read signals as a default read signal based, at least in part, on the comparison.

16. The apparatus of claim 15, wherein the controller is configured to set one of the plurality of discrete read signals as the default read signal based at least in part on the comparison by setting the one of the plurality of discrete read signals that results in a fewest number of errors as the default read signal.

17. The apparatus of claim 15, wherein the controller is configured to use the default read signal and a signal among the plurality of discrete read signals as read signals to distinguish different data states.

18. The apparatus of claim 15, wherein reading the data comprises reading a particular type of page of data from the group of memory cells, wherein the particular type of pages of data is selected from the group including a lower page of data, a middle page of data, and an upper page of data.

19. The apparatus of claim 18, wherein the controller is configured to set one of the plurality of discrete read signals as the default read signal for the particular type of page data from the group of memory cells.

20. The apparatus of claim 15, wherein respective discrete read signals among the plurality of discrete signals have different magnitudes.