Security of program executables and microprocessors based on compiler-architecture interaction

• US 9,582,650 B2
• Filed: 11/21/2012
• Issued: 02/28/2017
• Est. Priority Date: 11/17/2003
• Status: Active Grant

• Current Assignee: BlueRISC Inc.
• Original Assignee: BlueRISC Inc.
• Inventors: Chheda, Saurabh, Carver, Kristopher, Ashok, Raksit
• Primary Examiner(s): Hirl, Joseph P
• Assistant Examiner(s): GYORFI, THOMAS A
• Application Number:
  US13/683,640
• Publication Number:
  US 20130326236A1
• Time in Patent Office: 1,560 Days
• Field of Search: 713/190, 712/209
• US Class Current: 1/1
• CPC Class Codes: G06F 21/125 by manipulating the program code, e.g. source code, compiled code, interpreted code, machine code
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30156 Special purpose encoding of instructions, e.g. Gray coding
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification

Abstract

A method, for use in a processor context, wherein instructions in a program executable are encoded with plural instruction set encodings. A method wherein a control instruction encoded with an instruction set encoding contains information about decoding of an instruction that is encoded with another instruction set encoding scheme. A method wherein instruction set encodings are randomly generated at compile time. A processor framework wherein an instruction is decoded during execution with the help of information provided by a previously decoded control instruction.

Claims

1. A processor comprising:

memory storing instructions for an instruction stream of a program executable, the instruction stream comprising blocks of instructions, a first block of instructions among the blocks of instructions having been encoded in a first instruction set architecture using a first technique, and a second block of instructions among the blocks of instructions having been encoded in a second instruction set architecture using a second technique, the first instruction set architecture being different from the second instruction set architecture, the instruction stream further comprising a first control instruction and a second control instruction, the first control instruction preceding the first block of instructions in the instruction stream, the first control instruction providing first information about the first technique, and the second control instruction preceding the second block of instructions in the instruction stream, the second control instruction providing second information about the second technique; and

a decoder to receive the instruction stream and to perform operations comprising;

receiving the first control instruction in the instruction stream;

obtaining, from the first control instruction, the first information about the first technique;

receiving the first block of instructions in the instruction stream;

using the first information to decode the first block of instructions to produce first decoded instructions;

outputting, in a pipeline of the processor, the first decoded instructions;

receiving the second control instruction in the instruction stream;

obtaining, from the second control instruction, the second information about the second technique;

receiving the second block of instructions in the instruction stream;

using the second information to decode the second block of instructions to produce second decoded instructions; and

outputting, in the pipeline of the processor, the second decoded instructions.

2. The processor of claim 1, wherein the pipeline comprises an execution stage to receive the first and second decoded instructions.

3. The processor of claim 1, wherein the first information is usable to configure the decoder to decode the first block of instructions, and the second information is usable to configure the decoder to decode the second block of instructions.

4. The processor of claim 1, wherein at least one of the first control instruction or the second control instruction comprises a co-processor instruction.

5. The processor of claim 1, further comprising:

memory storing a compiler to perform operations comprising;

generating the first block of instructions and the second block of instructions;

generating the first control instruction and the second control instruction; and

generating the instruction stream from the first control instruction, the second control instruction, the first block of instructions, and the second block of instructions.

6. The processor of claim 1, wherein a third block of instructions among the blocks of instructions has been encoded in a third instruction set architecture using a third technique, the third instruction set architecture being different from both the first instructions set architecture and the second instruction set architecture, the instruction stream further comprising a third control instruction that precedes the third block of instructions in the instruction stream, the third control instruction providing third information about the third technique;

and

wherein the decoder is configured to perform operations comprising;

receiving the third control instruction in the instruction stream;

obtaining, from the third control instruction, the third information about the third technique;

receiving the third block of instructions in the instruction stream;

using the third information to decode the third block of instructions to produce third decoded instructions; and

outputting, in the pipeline of the processor, the third decoded instructions.

7. The processor of claim 1, wherein the first technique comprises a process according to which bits of the first block of instructions are coded, and the second technique comprises a process according to which bits of the second block of instructions are coded.

8. The processor of claim 1, wherein at least one of the first or second control instructions is coded using keys.

9. The processor of claim 1, wherein at least some of the blocks of instructions are scrambled for security and comprise flipped bits, rotated bits, or a combination of flipped bits and rotated bits.

10. The processor of claim 1, wherein the decoder comprises a static decode part to decode control instructions and an instruction decode part to decode blocks of instructions.

11. The processor of claim 1, further comprising memory to store a compiler configured to affect redundant activity in a data cache by leveraging static information about data access patterns in the processor that are available at compile time.