High speed processing of financial information using FPGA devices

• US 9,582,831 B2
• Filed: 03/31/2011
• Issued: 02/28/2017
• Est. Priority Date: 06/19/2006
• Status: Active Grant

• Current Assignee: Exegy Incorporated
• Original Assignee: Ip Reservoir, LLC
• Inventors: Parsons, Scott, Taylor, David E., Schuehler, David Vincent, Franklin, Mark A., Chamberlain, Roger D.
• Primary Examiner(s): Borlinghaus, Jason M
• Application Number:
  US13/076,968
• Publication Number:
  US 20110178918A1
• Time in Patent Office: 2,161 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06Q 40/00 Finance; Insurance; Tax strategies; Processing of corporate or income taxes
• CPC Class Codes: G06Q 40/04 Trading; Exchange, e.g. stocks, commodities, derivatives or currency exchange
• CPC Class Codes: G06Q 40/06 Asset management; Financial planning or analysis

Abstract

A high speed system and method for processing financial instrument order data are disclosed. With respect to an exemplary embodiment, a reconfigurable logic device is employed to monitor a financial instrument order based on a risk profile to determine whether the order is appropriate. If determined appropriate, a financial instrument order can be routed to a trading venue. With respect to another exemplary embodiment, a reconfigurable logic device is employed to maintain a financial instrument order book.

Claims

1. An apparatus comprising:

an order management system (OMS) configured to manage a plurality of streaming buy and sell orders for a plurality of financial instruments, the OMS comprising (1) a processor, and (2) a reconfigurable logic device having firmware logic deployed thereon, the firmware logic comprising a firmware socket module and a firmware application module pipeline;

wherein the processor is configured to (1) execute an operating system, the operating system including a user space for a user mode and a kernel space for a kernel mode, (2) receive the streaming orders as traffic through a protocol stack, and (3) process the streaming orders from the protocol stack within the kernel space while in the kernel mode without requiring a transition to the user mode;

wherein the firmware socket module is configured to (1) stream the streaming orders into the reconfigurable logic device from memory outside the reconfigurable logic device via DMA operations, and (2) provide the streaming orders to the firmware application module pipeline; and

wherein the firmware application module pipeline is configured to (1) receive the streaming orders, (2) compare the steaming orders against a plurality of risk profiles, and (3) based on the comparison, determine whether any of the streaming orders are appropriate.

2. The apparatus of claim 1 further comprising an order router configured to route streaming orders that are determined to be appropriate to a trading venue.

3. The apparatus of claim 2 further comprising a memory in which a plurality of financial instrument order books are stored, the order books comprising sorted lists of pricing information for a plurality of financial instrument orders, and wherein the firmware logic is further configured to update the order books in real-time based on streaming financial market data.

4. The apparatus of claim 3 wherein the order router is further configured to route the streaming orders that are determined to be appropriate to a trading venue based on a plurality of criteria associated with the streaming orders.

5. The apparatus of claim 4 wherein the order router is further configured to route the streaming orders that are determined to be appropriate to a trading venue based on a plurality of criteria associated with the streaming orders and associated with at least one user or application that submitted the streaming orders.

6. The apparatus of claim 5 further comprising a trading engine configured to subdivide a streaming order determined to be appropriate into a plurality of smaller orders prior to the smaller orders being routed to a trading venue.

7. The apparatus of claim 2 wherein the order router is implemented in firmware logic deployed on the reconfigurable logic device, and wherein the OMS and the order router are configured to operate simultaneously in a pipeline fashion such that the OMS operates on newly received streaming orders while the order router operates on streaming orders previously processed by the OMS.

8. The apparatus of claim 2 wherein the firmware application module pipeline is further configured to perform the routing operation, and wherein the firmware application module pipeline is configured to perform the OMS operations and the routing operations simultaneously in a pipelined fashion.

9. The apparatus of claim 2 wherein the firmware application module pipeline is further configured to compare the steaming orders against a plurality of risk profiles and a plurality of credit profiles to determine whether any of the streaming orders are appropriate.

10. The apparatus of claim 9 wherein each streaming order is associated with an account owner, and wherein the firmware application module pipeline is further configured to compare the steaming orders against a plurality of risk profiles, a plurality of credit profiles, and an account status associated with the account owner to determine whether any of the streaming orders are appropriate.

11. The apparatus of claim 10 wherein the OMS further comprises a data store for storing account information and an archive of previous financial instrument orders, and wherein the firmware application module pipeline is configured to perform the comparison operation supported by data accessed from the data store.

18. The apparatus of claim 1 wherein the firmware socket module is further configured to provide both command data and the streaming orders to the firmware application module pipeline, wherein the firmware application module pipeline is further configured arrange itself in accordance with the command data to control how the comparison operation is performed.

19. The apparatus of claim 18 further comprising a bus, wherein the processor and the reconfigurable logic device are in communication with the bus, wherein the reconfigurable logic device is further configured to access the command data and the streaming orders via the bus, and wherein the processor is further configured to generate the command data.

20. The apparatus of claim 1 wherein the processor is further configured to directly route the streaming orders for delivery to the reconfigurable logic device without a transition to the user mode.

33. The apparatus of claim 1 wherein the processor further comprises a driver that includes a kernel mode interface into the protocol stack, the driver configured to read the streaming orders out of the protocol stack while in the kernel mode via the kernel mode interface.

12. An order management method, the method comprising:

managing a plurality of streaming buy and sell orders for a plurality of financial instruments using an order management system (OMS), the OMS comprising (1) a processor, and (2) a reconfigurable logic device having firmware logic deployed thereon, the firmware logic comprising a firmware socket module and a firmware application module pipeline, wherein the managing step comprises;

the processor (1) executing an operating system, the operating system including a user space for a user mode and a kernel space for a kernel mode, (2) receiving the streaming orders as traffic through a protocol stack, and (3) processing the streaming orders from the protocol stack within the kernel space while in the kernel mode without requiring a transition to the user mode;

the firmware socket module (1) streaming the streaming orders into the reconfigurable logic device from memory outside the reconfigurable logic device via DMA operations, and (2) providing the streaming orders to the firmware application module pipeline; and

the firmware application module pipeline (1) receiving the streaming orders, (2) comparing the steaming orders against a plurality of risk profiles, and (3) based on the comparing, determining whether any of the streaming orders are appropriate.

13. The method of claim 12 wherein the firmware application module pipeline, the method further comprising:

the order router routing streaming orders that are determined to be appropriate to a trading venue; and

wherein the firmware application module simultaneously performs the comparing, determining, and routing steps in a pipelined fashion such that the comparing and determining steps are performed on new streaming orders while the routing step is performed on previous streaming orders that were previously determined to be appropriate.

21. The method of claim 12 wherein the streaming step further comprises the firmware socket module providing both command data and the streaming orders to the firmware application module pipeline, the method further comprising:

the firmware application module pipeline arranging itself in accordance with the command data to control how the comparing step is performed.

22. The method of claim 21 wherein the reconfigurable logic device is in communication with the processor via a bus, the method further comprising:

the reconfigurable logic device accessing the command data and the streaming orders via the bus; and

the processor generating the command data.

23. The method of claim 12 further comprising the processor directly routing the streaming orders for delivery to the reconfigurable logic device without transitioning to the user mode.

34. The method of claim 12 wherein the processor further comprises a driver that includes a kernel mode interface into the protocol stack, and wherein the processing step comprises the driver reading the streaming orders out of the protocol stack while in the kernel mode via the kernel mode interface.

14. An apparatus comprising:

a computer system comprising a processor and a reconfigurable logic device that are configured to cooperate with each other to process streaming financial market data relating to a plurality of financial instruments and manage a delivery of the processed financial market data for consumption by a plurality of clients;

wherein the processor is configured to execute an operating system, the operating system including a user space for a user mode and a kernel space for a kernel mode;

wherein the reconfigurable logic device is configured to (1) perform a processing operation on the streaming financial market data to thereby generate processed financial market data and (2) stream the processed financial market data out of the reconfigurable logic device into a memory within the kernel space of the operating system via DMA operations; and

wherein a driver that executes within the kernel space of the operating system while the operating system is in the kernel mode is configured to (1) read the processed financial market data from the memory, and (2) selectively route the processed financial market data for delivery to the clients via a path that is wholly within the kernel space.

15. The apparatus of claim 14 wherein the reconfigurable logic device comprises a field programmable gate array (FPGA).

16. The apparatus of claim 15 wherein the processor comprises a general purpose processor (GPP).

24. The apparatus of claim 14 wherein the operating system comprises a network protocol stack through which the computer system receives a feed of the streaming financial market data;

wherein another driver that executes within the kernel space of the operating system while the operating system is in the kernel mode is configured to (1) maintain a kernel level interface into the network protocol stack, and (2) copy the streaming financial market data from the network protocol stack into a shared memory that is mapped into the kernel space and the user space; and

wherein user mode code that executes within the user space of the operating system is configured to access financial market data from the shared memory and perform a processing operation on the accessed financial market data.

25. The apparatus of claim 24 wherein the reconfigurable logic device comprises a firmware socket module and a firmware application module pipeline;

wherein the firmware socket module is configured to (1) stream the normalized financial market data into the reconfigurable logic device from the shared memory via DMA operations, and (2) provide the streaming normalized financial market data to the firmware application module pipeline; and

wherein the firmware application module pipeline is configured to perform the processing operation on the streaming normalized financial market data to generate the processed financial market data.

26. The apparatus of claim 25 wherein the firmware socket module is further configured to provide both command data and the streaming normalized financial market data to the firmware application module pipeline, wherein the firmware application module pipeline is further configured arrange itself in accordance with the command data to control how the processing operation is performed.

27. The apparatus of claim 26 further comprising a bus, wherein the processor and the reconfigurable logic device are in communication via the bus, wherein the reconfigurable logic device is further configured to access the command data and the streaming normalized financial market data via the bus, and wherein the processor is further configured to generate the command data.

28. The apparatus of claim 14 wherein the driver is further configured to directly route the processed financial market data to a destination within the kernel space while the operating system is in the kernel mode without a transition to the user mode, the destination being associated with a client.

35. The apparatus of claim 14 wherein the operating system comprises a network protocol stack through which a plurality of the clients connect with the computer system to access processed financial market data;

and

wherein the driver is further configured to maintain a kernel level interface into the network protocol stack and deliver the processed financial market data to the network protocol stack through the kernel level interface while the operating system is in the kernel mode.

36. The apparatus of claim 14 wherein the driver comprises a first driver and a second driver, wherein the first and second drivers define the path wholly within the kernel space for delivery of the processed financial market data from the reconfigurable logic device to the clients without a transition by the operating system from the kernel mode to the user mode as part of the delivery;

wherein the first driver is configured to read the processed financial market data from the memory; and

wherein the second driver is configured to selectively route the processed financial market data within the kernel space for delivery to the clients.

37. The apparatus of claim 24 wherein the user mode code comprises a plurality of threads configured to (1) normalize the accessed financial market data, and (2) write the normalized financial market data to additional shared memory that is mapped into the kernel space and the user space;

wherein the driver comprises a hardware interface driver, the hardware interface driver configured facilitate DMA transfers of the normalized financial market data from the additional shared memory into the reconfigurable logic device; and

wherein the reconfigurable logic device is further configured to (1) stream in the normalized financial market data via DMA transfers from the additional shared memory, and (2) perform the processing operation on the streaming normalized financial market data to generate the processed financial market data.

38. The apparatus of claim 37 wherein the processing operation performed by the reconfigurable logic device comprises a member of the group consisting of (1) a last value cache (LVC) operation, (2) an order book maintenance operation, and (3) an interest and entitlement filtering operation.

39. The apparatus of claim 14 wherein the computer system comprises a ticker plant.

45. The apparatus of claim 24 wherein the shared memory comprises a ring buffer.

46. The apparatus of claim 37 wherein the additional shared memory comprises a ring buffer.

17. A method for processing financial market data using a system comprising a processor and a reconfigurable logic device, the method comprising:

the processor executing an operating system, the operating system including a user space for a user mode and a kernel space for a kernel mode, wherein the executing step comprises;

a network protocol stack executed by the operating system receiving a feed of streaming financial market data for a plurality of financial instruments;

a first driver executed within the kernel space of the operating system while the operating system is in the kernel mode (1) maintaining a kernel level interface into the network protocol stack, and (2) copying the streaming financial market data from the network protocol stack into a shared memory that is mapped into the kernel space and the user space, wherein the copying is performed by the driver without the operating system transitioning to the user mode;

user mode code executed within the user space of the operating system (1) accessing the financial market data from the shared memory, (2) normalizing the accessed financial market data, and (3) writing the normalized financial market data to additional shared memory that is mapped into the kernel space and the user space; and

a second driver executed within the kernel space of the operating system while the operating system is in the kernel mode facilitating DMA transfers of the normalized financial market data from the additional shared memory into the reconfigurable logic device;

the reconfigurable logic device streaming the normalized financial market data into the reconfigurable logic device from the additional shared memory via DMA operations, the reconfigurable logic device having a resident firmware pipeline; and

the firmware pipeline (1) receiving the streaming normalized financial market data, and (2) performing a processing operation on the received streaming normalized financial market data to generate processed financial market data for delivery to a plurality of clients.

29. The method of claim 17 wherein the reconfigurable logic device further comprises a firmware socket module, the method further comprising:

the firmware socket module (1) streaming the normalized financial market data into the reconfigurable logic device from the additional shared memory via DMA operations, and (2) providing the streaming normalized financial market data to the firmware pipeline.

30. The method of claim 29 wherein the streaming step further comprises the firmware socket module providing both command data and the streaming normalized financial market data to the firmware pipeline, the method further comprising:

the firmware pipeline arranging itself in accordance with the command data to control how the processing operation is performed.

31. The method of claim 30 wherein the reconfigurable logic device is in communication with the processor via a bus, the method further comprising:

the reconfigurable logic device accessing the command data and the streaming normalized financial market data via the bus; and

the processor generating the command data.

32. The method of claim 17 wherein the executing step further comprises the processor directly routing the processed financial market data for delivery to the clients without the operating system transitioning to the user mode as part of the routing.

40. The method of claim 17 wherein the user mode code comprises a plurality of threads, each thread executing to normalize a different group of the accessed financial market data independently of the other threads.

41. The method of claim 17 wherein the reconfigurable logic device comprises a field programmable gate array (FPGA).

42. The method of claim 17 wherein the processor and reconfigurable logic device are part of a ticker plant.

43. The method of claim 17 wherein the shared memory comprises a ring buffer.

44. The method of claim 17 wherein the additional shared memory comprises a ring buffer.