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Low power memory cell with high sensing margin

  • US 9,583,167 B2
  • Filed: 04/29/2015
  • Issued: 02/28/2017
  • Est. Priority Date: 04/29/2015
  • Status: Active Grant
First Claim
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1. A memory cell comprising:

  • a first magnetic tunnel junction (MTJ) element coupled to a first bit line;

    a second MTJ element coupled to a second bit line, wherein the first and second MTJ elements have a common node;

    a first selector having a first selector first select transistor with a first gate coupled to a first wordline and first and second source/drain (S/D) regions, wherein the common node of the first and second MTJ elements is coupled to the first S/D region of the first selector first select transistor; and

    a second selector having a second selector first select transistor with a second gate coupled to a second wordline and first and second S/D regions, and a second selector second select transistor with a third gate coupled to the second wordline and first and second S/D regions, wherein the first S/D regions of the second selector first select transistor and second selector second select transistor are a common first S/D region coupled to the second bitline.

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