Low power memory cell with high sensing margin
First Claim
Patent Images
1. A memory cell comprising:
- a first magnetic tunnel junction (MTJ) element coupled to a first bit line;
a second MTJ element coupled to a second bit line, wherein the first and second MTJ elements have a common node;
a first selector having a first selector first select transistor with a first gate coupled to a first wordline and first and second source/drain (S/D) regions, wherein the common node of the first and second MTJ elements is coupled to the first S/D region of the first selector first select transistor; and
a second selector having a second selector first select transistor with a second gate coupled to a second wordline and first and second S/D regions, and a second selector second select transistor with a third gate coupled to the second wordline and first and second S/D regions, wherein the first S/D regions of the second selector first select transistor and second selector second select transistor are a common first S/D region coupled to the second bitline.
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Abstract
Memory cell, method for operating the memory cell and method of forming the memory cell are disclosed. The memory cell includes a first selector having a first select transistor with a first gate coupled to a first wordline and first and second source/drain (S/D) regions, and a second selector having at least a second select transistor with a second gate coupled to a second wordline and first and second S/D regions. The memory cell includes a first magnetic tunnel junction (MTJ) element coupled between a first bit line and the first S/D region of the first select transistor, and a second MTJ element coupled between a second bit line and the first S/D region of the second select transistor.
51 Citations
20 Claims
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1. A memory cell comprising:
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a first magnetic tunnel junction (MTJ) element coupled to a first bit line; a second MTJ element coupled to a second bit line, wherein the first and second MTJ elements have a common node; a first selector having a first selector first select transistor with a first gate coupled to a first wordline and first and second source/drain (S/D) regions, wherein the common node of the first and second MTJ elements is coupled to the first S/D region of the first selector first select transistor; and a second selector having a second selector first select transistor with a second gate coupled to a second wordline and first and second S/D regions, and a second selector second select transistor with a third gate coupled to the second wordline and first and second S/D regions, wherein the first S/D regions of the second selector first select transistor and second selector second select transistor are a common first S/D region coupled to the second bitline. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of operating a memory cell comprising:
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providing a memory cell comprising a first magnetic tunnel junction (MTJ) element coupled to a first bit line; a second MTJ element coupled to a second bit line, wherein the first and second MTJ elements have a common node; a first selector having a first selector first select transistor with a first gate terminal coupled to a first wordline and first and second S/D terminals, wherein the common node of the first and second MTJ elements is coupled to the first S/D terminal of the first selector first select transistor, a second selector having a second select transistor with a second gate terminal coupled to a second wordline and first and second S/D terminals, a third select transistor with a third gate terminal coupled to the second wordline and first and second S/D terminals, wherein the first S/D terminals of the second and third select transistors are a common first S/D terminal; and performing a read operation or write operation with the memory cell. - View Dependent Claims (8, 9)
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10. A method of operating a memory cell comprising:
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providing a memory cell comprising a first selector having a first select transistor with a first gate terminal coupled to a read wordline and first and second S/D terminals, a second selector having a second select transistor with a second gate terminal coupled to a write wordline and first and second S/D terminals, a third select transistor with a third gate terminal coupled to the write wordline and first and second S/D terminals, wherein the first S/D terminals of the second and third select transistors are a common first S/D terminal, wherein the second S/D terminals of the first and second select transistors are coupled to a common source line, a first magnetic tunnel junction (MTJ) element coupled between a first bit line and the first S/D terminal of the first select transistor, and a second MTJ element coupled to a second bit line and the first S/D terminals of the second and third select transistors; and performing a read operation or write operation with the memory cell, wherein performing a write operation comprises; providing an active write signal to the write wordline and providing an inactive signal to the read wordline; and forming a write path from the first bitline to source line by floating the second bitline. - View Dependent Claims (11)
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12. A method for forming a memory cell comprising:
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providing a cell selector unit on a substrate comprising forming a first selector having a first selector first select transistor with a first gate and first and second S/D regions, forming a second selector which comprises forming a second selector first select transistor with a second gate and first and second S/D regions, and a second selector second select transistor with a third gate and first and second S/D regions; providing a cell dielectric layer on the substrate; forming a storage unit in the cell dielectric layer which comprises forming first and second magnetic tunnel junction (MTJ) elements; forming an upper metal level over the cell dielectric layer which comprises forming first and second bitlines in the upper metal level; coupling the first gate of the first selector first select transistor to a first wordline; coupling the second and third gates of the second selector first select transistor and second selector second select transistor to a second wordline; coupling the first MTJ element between the first bit line and the first S/D region of the first selector first select transistor; and coupling the second MTJ element to the second bit line and the first S/D region of the second selector first select transistor. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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Specification