Write driver circuits for resistive random access memory (RAM) arrays
First Claim
1. A write driver circuit for writing data to a resistive random access memory (RAM) array, comprising:
- an isolation circuit coupled to;
a current source; and
a selector circuit configured to select one or more resistive RAM bitcells in a resistive RAM array for a write operation; and
a precharging circuit coupled to a precharge voltage source and the selector circuit;
wherein the isolation circuit is configured to;
receive a control signal;
couple the current source to the selector circuit to provide a write voltage to the one or more resistive RAM bitcells selected by the selector circuit if the control signal indicates a write state for the write operation; and
decouple the current source from the selector circuit if the control signal does not indicate the write state;
wherein the precharging circuit is configured to;
couple the precharge voltage source to the selector circuit to provide a precharge voltage to a plurality of coupling elements in the selector circuit if the control signal indicates a precharge state for precharging the selector circuit; and
decouple the precharge voltage source from the plurality of coupling elements in the selector circuit if the control signal does not indicate the precharge state for precharging the selector circuit.
1 Assignment
0 Petitions
Accused Products
Abstract
Aspects disclosed in the detailed description include write driver circuits for resistive random access memory (RAM) arrays. In one aspect, a write driver circuit is provided to facilitate writing data into a resistive RAM array in a memory system. The write driver circuit is coupled to a selector circuit configured to select a memory bitcell(s) in the resistive RAM array for a write operation. An isolation circuit is provided in the write driver circuit to couple a current source to the selector circuit to provide a write voltage during the write operation and to isolate the current source from the selector circuit when the selector circuit is not engaged in the write operation. By isolating the selector circuit from the current source when the selector circuit is on standby, it is possible to reduce leakage current in the selector circuit, thus reducing standby power consumption in the memory system.
24 Citations
26 Claims
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1. A write driver circuit for writing data to a resistive random access memory (RAM) array, comprising:
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an isolation circuit coupled to; a current source; and a selector circuit configured to select one or more resistive RAM bitcells in a resistive RAM array for a write operation; and a precharging circuit coupled to a precharge voltage source and the selector circuit; wherein the isolation circuit is configured to; receive a control signal; couple the current source to the selector circuit to provide a write voltage to the one or more resistive RAM bitcells selected by the selector circuit if the control signal indicates a write state for the write operation; and decouple the current source from the selector circuit if the control signal does not indicate the write state; wherein the precharging circuit is configured to; couple the precharge voltage source to the selector circuit to provide a precharge voltage to a plurality of coupling elements in the selector circuit if the control signal indicates a precharge state for precharging the selector circuit; and decouple the precharge voltage source from the plurality of coupling elements in the selector circuit if the control signal does not indicate the precharge state for precharging the selector circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A means for writing data to a resistive random access memory (RAM) array, comprising:
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a means for isolation coupled to; a current source; and a selector circuit configured to select one or more resistive RAM bitcells in a resistive RAM array for a write operation; and a precharging circuit coupled to a precharge voltage source and the selector circuit; wherein the means for isolation is configured to; receive a control signal; couple the current source to the selector circuit to provide a write voltage to the one or more resistive RAM bitcells selected by the selector circuit if the control signal indicates a write state for the write operation; and decouple the current source from the selector circuit if the control signal does not indicate the write state; wherein the precharging circuit is configured to; couple the precharge voltage source to the selector circuit to provide a precharge voltage to a plurality of coupling elements in the selector circuit if the control signal indicates a precharge state for precharging the selector circuit; and decouple the precharge voltage source from the plurality of coupling elements in the selector circuit if the control signal does not indicate the precharge state for precharging the selector circuit.
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11. A method for providing a write voltage to a resistive random access memory (RAM) array during a write operation, comprising:
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receiving a control signal by an isolation circuit; coupling a current source to a selector circuit if the control signal indicates a write state, wherein the current source is configured to provide the write voltage to one or more resistive RAM bitcells selected by the selector circuit for the write operation; decoupling the current source from the selector circuit if the control signal does not indicate the write state; coupling a precharging circuit to the selector circuit to provide a precharge voltage to the selector circuit if the control signal indicates a precharge state; and decoupling the precharging circuit from the selector circuit if the control signal does not indicate the precharge state. - View Dependent Claims (12, 13, 14, 15)
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16. A resistive random access memory (RAM) system, comprising:
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a resistive RAM array comprising a plurality of resistive RAM bitcells arranged into M rows and N columns, wherein M and N are finite integers; wherein each of the M rows comprises N resistive RAM bitcells coupled to a respective word line (WL); wherein each of the N columns comprises M resistive RAM bitcells coupled to a respective bit line (BL) and a respective source line (SL); a selector circuit comprising N coupling elements, wherein each of the N coupling elements is configured to be coupled to a respective column among the N columns in the resistive RAM array for a write operation; a write driver circuit comprising an isolation circuit coupled to the selector circuit and a current source; wherein the isolation circuit is configured to; receive a control signal; couple the current source to the selector circuit to provide a write voltage to one or more resistive RAM bitcells selected by the selector circuit if the control signal indicates a write state for the write operation; and decouple the current source from the selector circuit if the control signal does not indicate the write state; a precharging circuit coupled to the N coupling elements in the selector circuit; a precharge voltage source coupled to the precharging circuit; and an inverter, comprising; an input (I) terminal coupled to the isolation circuit; and an output (O) terminal coupled to the precharging circuit. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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Specification