Carbon layer and method of manufacture

• US 9,583,392 B2
• Filed: 06/30/2016
• Issued: 02/28/2017
• Est. Priority Date: 07/11/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: van Dal, Mark
• Primary Examiner(s): GREEN, TELLY D
• Application Number:
  US15/199,441
• Publication Number:
  US 20160365282A1
• Time in Patent Office: 243 Days
• Field of Search: 438/664, 257/E21.09, 257/E21.296
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02378 Silicon carbide
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02491 Conductive materials
• CPC Class Codes: H01L 21/02527 Carbon, e.g. diamond-like carbon
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/7806 involving the separation of the active layers from a substrate
• CPC Class Codes: H01L 29/1606 Graphene
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66045 Field-effect transistors
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A system and method for manufacturing a carbon layer is provided. An embodiment comprises depositing a first metal layer on a substrate, the substrate comprising carbon. A silicide is epitiaxially grown on the substrate, the epitaxially growing the silicide also forming a layer of carbon over the silicide. In an embodiment the carbon layer is graphene, and may be transferred to a semiconductor substrate for further processing to form a channel within the graphene.

Claims

1. A method comprising:

performing a first anneal on a substrate, the substrate having a metal layer adjacent a carbon-containing layer, the first anneal forming a metal-containing compound layer and a graphene layer;

after performing the first anneal, transferring the graphene layer to a device substrate, graphite not being formed prior to the transferring; and

forming an active device on the device substrate, the graphene layer forming a conductive layer of the active device.

2. The method of claim 1, wherein the first anneal is performed at a temperature between room temperature and about 800 C.

3. The method of claim 2, wherein the first anneal is performed for a time period between about 1 seconds and 5 minutes.

4. The method of claim 2, further comprising curing the graphene layer.

5. The method of claim 4, wherein the curing is performed using a second anneal.

6. The method of claim 5, wherein the second anneal is performed at a between 500°

C. and 1,100°

C.

7. The method of claim 6, wherein the second anneal is performed for a time between 0.1 seconds and about 5 minutes.

8. The method of claim 6, wherein the first anneal is performed at a lower temperature than the second anneal.

9. A method comprising:

forming a graphene layer on a carrier substrate, wherein forming the graphene layer comprises;

depositing a metal on the carrier substrate, the carrier substrate comprising a carbon-containing material; and

reacting the metal with the carbon-containing material by performing a first anneal on the metal and the carrier substrate to form a metal-containing compound layer and the graphene layer on the metal-containing compound layer;

transferring the graphene layer to a device substrate, graphite not being formed before the transferring;

transferring the graphene layer to a device substrate, graphite not being formed before the transferring;

forming a gate electrode proximate the graphene layer on the device substrate; and

forming a first contact and a second contact to the graphene layer on the device substrate, the first contact and the second contact being on opposite sides of the gate electrode.

10. The method of claim 9, wherein the carrier substrate is a (111) substrate.

11. The method of claim 9, wherein the carrier substrate is a silicon carbide substrate.

12. The method of claim 9, further comprising curing the graphene layer by performing a second anneal, the second anneal being performed at a higher temperature than the first anneal.

13. The method of claim 9, wherein the graphene layer has a thickness of 5 nm or less.

14. A method comprising:

reacting a metal with a carbon-containing substrate, the reacting forming a metal silicide and a graphene layer;

attaching the graphene layer to a device substrate, graphite not being formed before the attaching; and

forming an active device on the device substrate, the graphene layer being a conductive layer of the active device.

15. The method of claim 14, wherein the metal comprises nickel, platinum, cobalt, palladium, copper, or iron.

16. The method of claim 14, wherein the metal has a thickness between about 0.5 nm and about 10 nm.

17. The method of claim 14, wherein the graphene layer has a thickness of the graphene layer between about 1 monolayer and about 10 monolayers.

18. The method of claim 14, further comprising, prior to attaching, curing the graphene layer.

19. The method of claim 18, wherein the reacting comprises performing a first anneal and the curing comprises performing a second anneal, the first anneal being performed at a lower temperature than the second anneal.