Semiconductor device and manufacturing method thereof

• US 9,583,399 B1
• Filed: 04/13/2016
• Issued: 02/28/2017
• Est. Priority Date: 11/30/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, I-Sheng, Wu, Cheng-Hsien, Yeh, Chih Chieh
• Primary Examiner(s): Sarkar, Asok K
• Application Number:
  US15/098,073
• Time in Patent Office: 321 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66772 : Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/6681 : using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/7848 : the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7853 : the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/78618 : characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device includes first channel layers disposed over a substrate, a first source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the first channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the first channel layers. Each of the first channel layers includes a semiconductor wire made of a first semiconductor material. The semiconductor wire extends into the first source/drain region. The semiconductor wire in the first source/drain regions is wrapped around by a second semiconductor material.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming a stacked structure of first semiconductor layers and second semiconductor layers alternately stacked in a first direction over a substrate;

patterning the stacked structure into a fin structure;

forming a sacrificial gate structure over the fin structure such that the sacrificial gate structure covers a part of the fin structure while remaining parts of the fin structure remain exposed, the remaining parts being source/drain regions and the part of the fin structure covered by the sacrificial gate structure being a channel region;

removing the second semiconductor layers in the source/drain regions of the fin structure, such that the first semiconductor layers in the source/drain regions are exposed and are spaced apart from each other;

recessing the second semiconductor layers in the channel region in a second direction perpendicular to the first direction toward inside the sacrificial gate structure;

forming epitaxial source/drain structures on the exposed first semiconductor layers in the source/drain regions so that the epitaxial source/drain structures wrap around each of the exposed first semiconductor layers in the source/drain regions;

removing the sacrificial gate structure to expose the channel region of the fin structure;

removing the second semiconductor layers in the exposed channel region of the fin structure after removing the sacrificial gate structure so that the first semiconductor layers in the channel region are exposed; and

forming a gate dielectric layer and a gate electrode layer around the exposed first semiconductor layers in the channel region.

2. The method of claim 1, further comprising, after the horizontally recessing the second semiconductor layers, partially etching the exposed first semiconductor layers in the source/drain regions.

3. The method of claim 1, wherein the first semiconductor layers are made of Si or a Si-based compound.

4. The method of claim 3, wherein the second semiconductor layers are made of SiGe.

5. The method of claim 3, wherein the epitaxial source/drain structures include at least one of SiP, SiCP and SiC.

6. The method of claim 3, wherein the epitaxial source/drain structures include SiGe or Ge.

7. The method of claim 1, further comprising forming sidewall spacer layers on both sidewalls of the sacrificial gate structure,

wherein after the horizontally recessing the second semiconductor layers, at least one end face of the second semiconductor layers are located below one of the sidewall spacers.

8. The method of claim 1, wherein, in the removing the second semiconductor layers in the source/drain regions, the second semiconductor layers are removed by wet etching.

9. The method of claim 1, wherein, in the removing the second semiconductor layer in the exposed channel region, the second semiconductor layers are removed by wet etching.

10. A method of manufacturing a semiconductor device, comprising:

forming a stacked structure of first semiconductor layers and second semiconductor layers alternately stacked in a first direction over a substrate;

patterning the stacked structure into a first fin structure and a second fin structure;

forming a sacrificial gate structure over the first and second fin structures such that the sacrificial gate structure covers a part of the first fin structure and a part of the second fin structure, while remaining parts of the first and second fin structures remain exposed, the remaining parts being source/drain regions of the first and second fin structures, respectively, and the part of the first fin structure covered by the sacrificial gate structure being a channel region of the first fin structure and the part of the second fin structure covered by the sacrificial gate structure being a channel region of the second fin structure;

covering the second fin structure with a first protective layer;

removing the second semiconductor layers in the source/drain regions of the first fin structure, such that the first semiconductor layers in the source/drain regions of the first fin structure are exposed and are spaced apart from each other;

recessing the second semiconductor layers in the channel region of the first fin structure in a second direction perpendicular to the first direction toward inside the sacrificial gate structure;

forming first epitaxial source/drain structures on the exposed first semiconductor layers in the source/drain regions of the first fin structure so that the first epitaxial source/drain structures wrap around each of the exposed first semiconductor layers in the source/drain regions of the first fin structure;

removing the sacrificial gate structure over the first fin structure to expose the channel region of the first fin structure;

removing the second semiconductor layers in the exposed channel region of the first fin structure after removing the sacrificial gate structure so that the first semiconductor layers in the channel region of the first fin structure are exposed; and

forming a gate dielectric layer and a gate electrode layer around the exposed first semiconductor layers in the channel region of the first fin structure.

11. The method of claim 10, further comprising:

removing the first protective layer;

covering with a second protective layer the second fin structures from which the second semiconductor layers in the channel region of the second fin structure are removed;

removing the second semiconductor layers in the source/drain regions of the second fin structure, such that the first semiconductor layers in the source/drain regions of the second fin structure are exposed and are spaced apart from each other;

recessing the second semiconductor layers in the channel region of the second fin structure in the second direction toward inside the sacrificial gate structure;

forming second epitaxial source/drain structures on the exposed first semiconductor layers in the source/drain regions of the second fin structure so that the second epitaxial source/drain structures wrap around each of the exposed first semiconductor layers in the source/drain regions of the second fin structure;

removing the sacrificial gate structure over the second fin structure to expose the channel region of the second fin structure;

removing the second semiconductor layers in the exposed channel region of the second fin structure after removing the sacrificial gate structure so that the first semiconductor layers in the channel region of the second fin structure are exposed; and

forming a gate dielectric layer and a gate electrode layer around the exposed first semiconductor layers in the channel region of the second fin structure.

12. The method of claim 11, wherein the first semiconductor layers are made of Si or a Si-based compound.

13. The method of claim 12, wherein the second semiconductor layers are made of SiGe.

14. The method of claim 12, wherein:

the first epitaxial source/drain structures include SiGe or Ge, and

the second epitaxial source/drain structures include at least one of SiP, SiCP and SiC.

15. The method of claim 10, further comprising:

removing the first protective layer;

covering with a second protective layer the second fin structures from which the second semiconductor layers in the channel region of the second fin structure are removed;

forming second epitaxial source/drain structures over the first and second semiconductor layers in the source/drain regions of the second fin structure;

removing the sacrificial gate structure over the second fin structure to expose the channel region of the second fin structure;

removing the second semiconductor layers in the exposed channel region of the second fin structure after removing the sacrificial gate structure so that the first semiconductor layers in the channel region of the second fin structure are exposed; and

forming a gate dielectric layer and a gate electrode layer around the exposed first semiconductor layers in the channel region of the second fin structure.

16. The method of claim 15, wherein the first semiconductor layers are made of Si or a Si-based compound.

17. The method of claim 16, wherein the second semiconductor layers are made of SiGe.

18. The method of claim 16, wherein:

the first epitaxial source/drain structures include SiGe, and

the second epitaxial source/drain structures include at least one of SiP, SiCP and SiC.

19. A method of manufacturing a semiconductor device, comprising:

forming a stacked structure of first semiconductor layers and second semiconductor layers alternately stacked in a first direction over a substrate;

patterning the stacked structure into a fin structure;

forming a sacrificial gate structure over the fin structure such that the sacrificial gate structure covers a part of the fin structure while remaining parts of the fin structure remain exposed, the remaining parts being source/drain regions and the part of the fin structure covered by the sacrificial gate structure being a channel region;

removing the second semiconductor layers in the source/drain regions of the fin structure, such that the first semiconductor layers in the source/drain regions are exposed and are spaced apart from each other;

recessing the second semiconductor layers in the channel region in a second direction perpendicular to the first direction toward inside the sacrificial gate structure;

forming epitaxial source/drain structures on the exposed first semiconductor layers in the source/drain regions so that the epitaxial source/drain structures wrap around each of the exposed first semiconductor layers in the source/drain regions;

removing the sacrificial gate structure to expose the channel region of the fin structure;

partially removing the second semiconductor layers in the exposed channel region of the fin structure after removing the sacrificial gate structure so that part of the first semiconductor layers in the channel region are exposed; and

forming a gate dielectric layer and a gate electrode layer around the exposed first semiconductor layers and remaining second semiconductor layers in the channel region.

20. The method of claim 19, further comprising, after the horizontally recessing the second semiconductor layers, partially etching the exposed first semiconductor layers in the source/drain regions.