Fine pitch BVA using reconstituted wafer with area array accessible for testing

• US 9,583,411 B2
• Filed: 01/17/2014
• Issued: 02/28/2017
• Est. Priority Date: 01/17/2014
• Status: Active Grant

• Current Assignee: Invensas LLC (Adeia Inc.)
• Original Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Inventors: Katkar, Rajesh
• Primary Examiner(s): Payen, Marvin
• Application Number:
  US14/157,790
• Publication Number:
  US 20150206815A1
• Time in Patent Office: 1,138 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/566 Release layers for moulds, e.g. release layers, layers against residue during moulding
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/68372 used to support a device or wafer when forming electrical connections thereto
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/83005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/92242 the first connecting process involving a layer connector
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1041 : Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/10 : the devices having separate containers
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15321 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19107 : off-chip wires

Abstract

A method for simultaneously making a plurality of microelectronic packages by forming an electrically conductive redistribution structure along with a plurality of microelectronic element attachment regions on a carrier. The attachment regions being spaced apart from one another and overlying the carrier. The method also including the formation of conductive connector elements between adjacent attachment regions. Each connector element having the first or second end adjacent the carrier and the remaining end at a height of the microelectronic element. The method also includes forming an encapsulation over portions of the connector elements and subsequently singulating the assembly, into microelectronic units, each including a microelectronic element. The surface of the microelectronic unit, opposite the redistribution structure, having both the active face of the microelectronic element and the free ends of the connector elements so that both are available for connection with a component external to the microelectronic unit.

Claims

1. A method for simultaneously making a plurality of microelectronic units, comprising the steps of:

providing an electrically conductive redistribution structure on a carrier and providing a plurality of microelectronic element attachment regions spaced apart from one another in at least a first direction parallel with a surface of the carrier;

forming a plurality of electrically conductive connector elements between adjacent attachment regions, each connector element having a first end, a second end and edge surfaces extending vertically between the first and second ends, the first end of each connector element being adjacent the redistribution structure and the second end of each connector element at a height greater than 50 microns above the carrier;

forming a dielectric encapsulation between adjacent edge surfaces of the connector elements;

further processing including singulating to form a plurality of microelectronic units, each microelectronic unit including a microelectronic element having a first face which faces away from the redistribution structure, and the microelectronic element having element contacts at the first face which are configured for joining with corresponding component contacts of a component external to the microelectronic unit through electrically conductive masses in a state in which the element contacts are juxtaposed with the corresponding component contacts.

2. The method of claim 1, wherein forming the plurality of electrically conductive connector elements comprises forming wire bonds attached to pads of the redistribution structure.

3. The method of claim 1, wherein forming the dielectric encapsulation comprises flowing a mold compound into a cavity of a mold to surround the connector elements in a state in which portions of the connector elements are covered by a film, and thereafter removing the film such that the second ends of the connector elements project above the surface of the dielectric encapsulation.

4. The method of claim 1, wherein forming the dielectric encapsulation includes:

forming the dielectric encapsulation over the second ends of the connector elements and adjacent sidewalls of the microelectronic elements; and

removing the dielectric encapsulation overlying the second ends such that the second ends of the connector elements project above the surface of the dielectric encapsulation.

22. The method of claim 2, wherein the electrically conductive connector elements are the wire bonds, the second ends of the connector elements are defined by ends of the wire bonds, the encapsulation has a surface overlying and facing away from the redistribution structure, wherein the second ends of the connector elements project above the surface.

5. A method for simultaneously making a plurality of microelectronic units, comprising the steps of:

providing a carrier with a plurality of microelectronic element attachment regions spaced apart from one another in at least a first direction parallel with a surface of the carrier;

forming a plurality of electrically conductive connector elements between adjacent attachment regions, each connector element having a first end, a second end and edge surfaces extending vertically between the first and second ends, the first end of each connector element being adjacent the carrier and the second end of each connector element at a height greater than 50 microns above the carrier;

attaching a plurality of microelectronic elements to respective attachment regions on the carrier, each microelectronic element having a first face, a second face and sidewalls extending between the first face and the second face, the first face having contacts and facing the carrier;

forming a dielectric encapsulation between adjacent edge surfaces of the connector elements;

forming an electrically conductive redistribution structure overlying at least a surface of the encapsulation opposite from the first face of the microelectronic element, the redistribution structure coupled to the second ends of the connector elements and having traces extending in at least the first direction;

singulating into a plurality of microelectronic units each including a microelectronic element, a side of the microelectronic unit having the first face of the microelectronic element and the first ends of the connector elements available for connection with a component external to the microelectronic unit.

6. The method of claim 5, wherein forming the plurality of electrically conductive connector elements includes:

forming a conductive layer overlying the carrier;

patterning the conductive layer to form pads; and

attaching a wire bond or forming a conductive mass on the pads.

7. The method of claim 5, wherein forming the dielectric encapsulation comprises film assist molding wherein the second end of the connector element projects above a surface of the encapsulant.

8. The method of claim 5, wherein forming the dielectric encapsulation includes forming the dielectric encapsulation over the second ends of the connector elements and subsequently removing the dielectric encapsulation from the second ends.

9. The method of claim 5, wherein the electrically conductive connector elements are free of electrical connections to the microelectronic element.

10. A microelectronic package having a first side and a second side opposite from the first side, the package comprising:

a microelectronic element having a first face, a second face opposite the first face, a plurality of sidewalls each extending between the first and second faces, and a plurality of element contacts at the first face;

an encapsulation adjacent the sidewalls of the microelectronic element and having a thickness in a direction between the first and second sides of the package, wherein the element contacts are configured for joining with corresponding component contacts of a component external to the microelectronic package in a state in which the element contacts are juxtaposed with the corresponding component contacts; and

electrically conductive connector elements each having a first end, a second end remote from the first end, and an edge surface extending between the first and second ends, wherein one of the first end or the second end of each connector element is adjacent the first side of the package and the other of the first end or the second end of each connector element is adjacent the second side of the package, the connector elements being contacted by the encapsulation between the first and second ends, the connector elements configured for electrically coupling a first external component adjacent the first side with a second external component adjacent the second side.

11. The microelectronic package of claim 10, further comprising a redistribution structure having terminals, the redistribution structure adjacent the second side of the package and opposite the first face of the microelectronic element, the terminals being electrically coupled with the connector elements, the terminals laterally spaced apart from the connector elements to which the terminals are electrically coupled, respectively.

12. The microelectronic package of claim 11, wherein the encapsulation has a surface overlying and facing away from the redistribution structure, the first end of a given connector element is adjacent the redistribution structure and the second end of a given connector element is at the first side of the package and protrudes beyond the surface of the encapsulation.

13. The microelectronic package of claim 11, wherein the first end of a given connector element is at the first side of the package, and the second end of the given connector element is adjacent the redistribution structure.

14. The microelectronic package of claim 10, wherein the first end of a given connector element is at the first side of the package, and the second end of the given connector element is at the second side of the package.

15. The package of claim 10, wherein the electrically conductive connector elements are free of electrical connections to the microelectronic element.

16. The microelectronic package of claim 10, wherein the connector elements are wire bonds.

17. The microelectronic package of claim 16, wherein the wire bonds have balls at the first ends.

18. The microelectronic package of claim 10, further comprising conductive joining masses formed at the first side of the microelectronic package, at least one conductive joining mass configured to electrically couple the microelectronic element to the first external component and at least one conductive joining mass configured to electrically couple the connector element to the first external component.

19. The microelectronic package of claim 10, wherein each connector element comprises a bond metal mass.

20. The microelectronic package of claim 10, wherein each connector element comprises a solder mass.

21. The microelectronic package of claim 20, wherein each connector element further comprises at least a portion of a pad to which the solder mass is joined.

23. The microelectronic package of claim 16, wherein the second ends of the connector elements are defined by ends of the wire bonds and the second ends project above the surface of the encapsulation.