2.5D electronic package

• US 9,583,431 B1
• Filed: 11/11/2014
• Issued: 02/28/2017
• Est. Priority Date: 11/28/2012
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Rahman, Arifur, Chandrasekar, Karthik
• Primary Examiner(s): Choi, Calvin
• Application Number:
  US14/538,646
• Time in Patent Office: 840 Days
• Field of Search: 257/691
• US Class Current: 1/1
• CPC Class Codes: G06F 2111/04 Constraint-based CAD
• CPC Class Codes: G06F 2111/06 Multi-objective optimisation, e.g. Pareto optimisation using simulated annealing [SA], ant colony algorithms or genetic algorithms [GA]
• CPC Class Codes: G06F 2113/18 Chip packaging
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 2119/08 Thermal analysis or thermal optimisation
• CPC Class Codes: G06F 2119/10 Noise analysis or noise optimisation
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H03K 19/177 : arranged in matrix form

Abstract

A 2.5D electronic package is provided in which at least one integrated circuit is mounted on an interposer that is mounted on a package substrate. To reduce warpage, the interconnection array of the integrated circuit does not include a thick metallization layer; and at least part of the power distribution function that would otherwise have been performed by the thick metallization layer is performed by one or more metallization layers that are added to the interposer. A method is provided for optimizing the design of the electronic package by choosing the appropriate number of metallization layers to be added to the interposer.

Claims

1. A device package comprising:

a package substrate having first and second major surfaces;

an integrated circuit having first and second major surfaces with a plurality of active devices formed in the first major surface, the integrated circuit being mounted in the package so that the first major surface of the integrated circuit faces the package substrate;

a first plurality of interconnection layers and intermetallic dielectric layers formed on the first major surface of the integrated circuit, an uppermost interconnect layer having a thickness no greater than that of any other interconnect layer; and

an interposer located between the integrated circuit and the package substrate with the integrated circuit mounted thereon, the interposer having at least one interconnection layer that is used primarily for power distribution in the integrated circuit, wherein the at least one interconnection layer that is used primarily for power distribution in the integrated circuit extends across an entire width of the interposer.

2. The device package of claim 1 wherein the interposer is a thin layer of a semiconductor material having first and second major surfaces and a plurality of conducting vias extending between the first and second major surfaces of the interposer.

3. The device package of claim 2 wherein the first plurality of interconnection layers are vertically stacked.

4. The device package of claim 1 wherein the integrated circuit is made of silicon, the interposer is a thin layer of silicon having first and second major surfaces and a plurality of through-silicon-vias provide conductive paths between the first and second major surfaces of the interposer.

5. The device package of claim 4 wherein the interposer has a thickness that is about 100 microns or less and the through-silicon-vias have a diameter that is about 10 microns or less.

6. The device package of claim 1 wherein the integrated circuit is mounted on the package substrate in flip-chip fashion.

7. The device package of claim 1 wherein the interposer is a thin, flat substrate having first and second major surfaces with interconnection layers on both major surfaces.

8. A device package comprising:

a package substrate having first and second major surfaces;

an integrated circuit having first and second major surfaces with a plurality of active devices formed in the first major surface, the integrated circuit being mounted in the package so that the first major surface of the integrated circuit faces the package substrate;

a first plurality of interconnection layers and intermetallic dielectric layers formed on the first major surface of the integrated circuit, an uppermost interconnect layer having a thickness no greater than that of any other interconnect layer on the integrated circuit; and

an interposer located between the integrated circuit and the package substrate with the integrated circuit mounted thereon, the interposer having at least one layer that is used primarily for power distribution in the integrated circuit, wherein the at least one layer that is used primarily for power distribution in the integrated circuit extends across an entire width of the interposer.

9. The device package of claim 8 wherein the interposer is a thin layer of a semiconductor material having first and second major surfaces and a plurality of conducting vias extending between the first and second major surfaces of the interposer.

10. The device package of claim 9 wherein the integrated circuit and the interposer are made of silicon.

11. The device package of claim 8 wherein the integrated circuit is made of silicon, the interposer is a thin layer of silicon having first and second major surfaces and a plurality of through-silicon-vias provide conductive paths between the first and second major surfaces of the interposer.

12. The device package of claim 11 wherein the interposer has a thickness that is about 100 microns or less and the through-silicon-vias have a diameter that is about 10 microns or less.

13. The device package of claim 8 wherein the integrated circuit is mounted on the package substrate in flip-chip fashion.

14. The device package of claim 8 wherein the interposer is a thin, flat substrate having first and second major surfaces with interconnection layers on both major surfaces.

15. A device package comprising:

a package substrate having first and second major surfaces;

an integrated circuit having first and second major surfaces with a plurality of active devices formed in the first major surface, the integrated circuit being mounted in the package so that the first major surface of the integrated circuit faces the package substrate;

a first plurality of interconnection layers and intermetallic dielectric layers formed on the first major surface of the integrated circuit, an uppermost interconnect layer having a thickness no greater than that of any other interconnect layer; and

an interposer located between the integrated circuit and the package substrate with the integrated circuit mounted thereon, the interposer being a flat substrate having first and second major surfaces with at least one interconnection layer on each major surface, wherein at least one layer in the interposer is used primarily for power distribution in the integrated circuit, and wherein the at least one layer in the interposer that is used primarily for power distribution in the integrated circuit extends across an entire width of the interposer.

16. The device package of claim 15 wherein the interposer is a thin layer of a semiconductor material having a plurality of conducting vias extending between the first and second major surfaces of the interposer.

17. The device package of claim 16 wherein the integrated circuit and the interposer are made of silicon.

18. The device package of claim 15 wherein the integrated circuit is made of silicon, the interposer is a thin layer of silicon and a plurality of through-silicon-vias provide conductive paths between the first and second major surfaces of the interposer.

19. The device package of claim 18 wherein the interposer has a thickness that is about 100 microns or less and the through-silicon-vias have a diameter that is about 10 microns or less.