Integrated device comprising stacked dies on redistribution layers

• US 9,583,460 B2
• Filed: 02/14/2014
• Issued: 02/28/2017
• Est. Priority Date: 02/14/2014
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Ray, Urmi, Gu, Shiqun
• Primary Examiner(s): PHAM, THANHHA S
• Application Number:
  US14/181,371
• Publication Number:
  US 20150235988A1
• Time in Patent Office: 1,110 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/73259 Bump and HDI connectors
• CPC Class Codes: H01L 2224/81005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/92224 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14335 : Digital signal processor [DSP]
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect

Abstract

Some features pertain to an integrated device that includes a dielectric layer configured as a base for the integrated device, several redistribution metal layers in the dielectric layer, a first wafer level die coupled to a first surface of the dielectric layer, and a second wafer level die coupled to the first wafer level die. The dielectric layer includes several dielectric layers. In some implementations, the first wafer level die is coupled to the redistribution metal layers through a first set of interconnects. In some implementations, the first wafer level die includes several through substrate vias (TSVs). In some implementations, the second wafer level die is coupled to the redistribution metal layers through a first set of interconnects, the TSVs, a second set of interconnects, and a set of solder balls. In some implementations, the integrated device includes an encapsulation layer that encapsulates the first and second wafer level dies.

Claims

1. An integrated device comprising:

a dielectric layer configured as a base for the integrated device;

a plurality of redistribution metal layers in the dielectric layer;

a first wafer level die coupled to a first surface of the dielectric layer, wherein the first wafer level die comprises at least one through substrate vias (TSVs);

a second wafer level die coupled to the first wafer level die, wherein the second wafer level die is coupled to the plurality of redistribution metal layers through a first set of interconnects adjacent to the dielectric layer and further wherein the first set of interconnects are metal pillars, wherein the second wafer level die is further coupled to the plurality of redistribution metal layers through the at least one through substrate vias of the first wafer level die, a second set of interconnects, and a set of solder balls, wherein the second set of interconnects are metal pillars; and

a third wafer level die coupled to the first surface of dielectric layer through a third set of interconnects wherein third set of interconnects are metal pillars and the third set of interconnects are vertically longer than the first set of interconnects.

2. The integrated device of claim 1, wherein the dielectric layer comprises several dielectric layers.

3. The integrated device of claim 1, wherein the first wafer level die is coupled to the plurality of redistribution metal layers through the first set of interconnects.

4. The integrated device of claim 1, wherein the second wafer level die is vertically coupled to the first wafer level die through the second set of interconnects, and the set of solder balls.

5. The integrated device of claim 1, further comprising an encapsulation layer that encapsulates the first wafer level die and the second wafer level die.

6. The integrated device of claim 1, wherein the first wafer level die is a processor and the second wafer level die is a memory die.

7. The integrated device of claim 1, wherein the integrated device is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.

8. The apparatus of claim 1, wherein the first wafer level die is a processor and the second wafer level die is a memory die.

9. An apparatus comprising:

a dielectric layer configured as a base for the integrated device;

a redistribution interconnect means in the dielectric layer;

a first wafer level die coupled to a first surface of the dielectric layer, wherein the first wafer level die comprises at least one through substrate vias (TSVs);

a second wafer level die coupled to the first wafer level die, wherein the second wafer level die is coupled to the redistribution interconnect means through a first set of interconnects adjacent to the dielectric layer and further wherein the first set of interconnects are metal pillars, wherein the second wafer level die is further coupled to the plurality of redistribution metal layers through the at least one through substrate via of the first wafer level die, a second set of interconnects, and a set of solder balls, wherein the second set of interconnects are metal pillars; and

a third wafer level die coupled to the first surface of dielectric layer through a third set of interconnects wherein third set of interconnects are metal pillars and the third set of interconnects are vertically longer than the first set of interconnects.

10. The apparatus of claim 9, wherein the dielectric layer comprises several dielectric layers.

11. The apparatus of claim 9, wherein the first wafer level die is coupled to the redistribution interconnect means through the first set of interconnects.

12. The apparatus of claim 9, wherein the second wafer level die is vertically coupled to first wafer level die through the second set of interconnects, and the set of solder balls.

13. The apparatus of claim 9, further comprising an encapsulation means that encapsulates the first wafer level die and the second wafer level die.

14. The apparatus of claim 9, wherein the apparatus is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.