Complete system-on-chip (SOC) using monolithic three dimensional (3D) integrated circuit (IC) (3DIC) technology

• US 9,583,473 B2
• Filed: 08/09/2016
• Issued: 02/28/2017
• Est. Priority Date: 07/16/2013
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Du, Yang
• Primary Examiner(s): NWUGO, OJIAKO K
• Application Number:
  US15/231,836
• Publication Number:
  US 20160351553A1
• Time in Patent Office: 203 Days
• Field of Search: 340 101- 105, 438/106, 438/121, 438/199, 438/627, 257/737, 257/751, 257/529, 257/209, 257/411
• US Class Current: 1/1
• CPC Class Codes: H01L 21/77 Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate electrically programmable read-only memories or multistep manufacturing processes therefor H10B69/00
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2225/06544 Design considerations for via connections, e.g. geometry or layout
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

Embodiments disclosed in the detailed description include a complete system-on-chip (SOC) solution using monolithic three dimensional (3D) integrated circuit (IC) (3DIC) integration technology. The present disclosure includes example of the ability to customize layers within a monolithic 3DIC and the accompanying short interconnections possible between tiers through monolithic intertier vias (MIV) to create a system on a chip. In particular, different tiers of the 3DIC are constructed to support different functionality and comply with differing design criteria. Thus, the 3DIC can have an analog layer, layers with higher voltage threshold, layers with lower leakage current, layers of different material to implement components that need different base materials and the like. Unlike the stacked dies, the upper layers may be the same size as the lower layers because no external wiring connections are required.

Claims

1. A monolithic three dimensional (3D) integrated circuit (IC) (3DIC) system, comprising:

a plurality of tiers positioned one on top of another;

a plurality of functional elements selected from the group consisting of;

computation, digital processing, analog processing, radio frequency (RF) signal processing, analog/mixed signal processing, power management, sensor, power supply, battery, memory, digital logic, low leakage, low noise/high gain, clock, combinatorial logic, and sequential logic;

the plurality of functional elements distributed amongst the plurality of tiers; and

a plurality of monolithic intertier vias (MIV) electrically coupling the plurality of tiers;

the plurality of functional elements providing a self-contained system on a chip (SOC).

2. The monolithic 3DIC system of claim 1, wherein each of the plurality of tiers has identical horizontal dimensions.

3. The monolithic 3DIC system of claim 1, wherein at least one tier of the plurality of tiers is optimized for high speed operation.

4. The monolithic 3DIC system of claim 1, wherein at least one tier of the plurality of tiers is optimized for low current leakage.

5. The monolithic 3DIC system of claim 1, wherein different ones of the plurality of functional elements are positioned on different ones of the plurality of tiers.

6. The monolithic 3DIC system of claim 1, wherein a first tier of the plurality of tiers comprises a first technology type configured to optimize a first function from the group.

7. The monolithic 3DIC system of claim 6, wherein a second tier of the plurality of tiers comprises a second technology type configured to optimize a second function from the group.

8. The monolithic 3DIC system of claim 1, wherein the plurality of tiers further comprises a third tier.

9. The monolithic 3DIC system of claim 1, wherein the monolithic 3DIC system operates as a RF transceiver.

10. The monolithic 3DIC of claim 1, further comprising a device selected from the group consisting of a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a mobile phone, a cellular phone, a computer, a portable computer, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, and a portable digital video player, into which the IC is integrated.

11. A monolithic three dimensional (3D) integrated circuit (IC) (3DIC) system, comprising:

a plurality of tiers positioned one on top of another;

means for providing a plurality of functions selected from the group consisting of;

computation, digital processing, analog processing, radio frequency (RF) signal processing, analog/mixed signal processing, power management, sensor, power supply, battery, memory, digital logic, low leakage, low noise/high gain, clock, combinatorial logic, and sequential logic;

the means for providing the plurality of functions distributed amongst the plurality of tiers; and

means to electrically intercouple the plurality of tiers;

the means for providing the plurality of functions providing a self-contained system on a chip (SOC).

12. The monolithic 3DIC system of claim 11, wherein the means to electrically intercouple the plurality of tiers comprise monolithic intertier vias (MIV).

13. The monolithic 3DIC system of claim 11, wherein the monolithic 3DIC system operates as a RF transceiver.

14. A method of implementing a three dimensional (3D) integrated circuit (IC) (3DIC) system, comprising:

providing a plurality of tiers within the 3DIC;

providing multiple functional elements across the plurality of tiers;

intercoupling the plurality of tiers using monolithic intertier vias (MIV); and

providing a self-contained system on a chip (SOC) with the 3DIC.

15. The method of claim 14, wherein providing the plurality of tiers comprises a plurality of tiers having identical horizontal dimensions.

16. The method of claim 14, wherein providing the plurality of tiers comprises providing at least one tier optimized for high speed operation.

17. The method of claim 14, wherein providing the plurality of tiers comprises providing at least one tier optimized for low current leakage.

18. The method of claim 14, wherein different ones of the multiple functional elements are positioned on different ones of the plurality of tiers.

19. The method of claim 14, wherein a first tier of the plurality of tiers comprises a first technology type configured to optimize a first function.

20. The method of claim 19, wherein a second tier of the plurality of tiers comprises a second technology type configured to optimize a second function.