Stacked half-bridge package

• US 9,583,477 B2
• Filed: 05/17/2016
• Issued: 02/28/2017
• Est. Priority Date: 01/14/2011
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Inventors: Cho, Eung San, Cheah, Chuan, Sawle, Andrew N.
• Primary Examiner(s): Clark, Sheila V.
• Application Number:
  US15/157,298
• Publication Number:
  US 20160260697A1
• Time in Patent Office: 287 Days
• Field of Search: 438/106, 438/107, 438/108, 438/109, 438/110, 438/111, 438/123
• US Class Current: 1/1
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/37147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/40095 Kinked
• CPC Class Codes: H01L 2224/40245 the item being metallic
• CPC Class Codes: H01L 2224/40247 Connecting the strap to a bond pad of the item
• CPC Class Codes: H01L 2224/73263 Layer and strap connectors
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 2224/84801 Soldering or alloying
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49524 the additional leads being a tape carrier or flat leads
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 24/36 Structure, shape, material or disposition of the strap connectors prior to the connecting process
• CPC Class Codes: H01L 24/37 of an individual strap connector
• CPC Class Codes: H01L 24/40 of an individual strap connector
• CPC Class Codes: H01L 24/41 of a plurality of strap connectors
• CPC Class Codes: H01L 24/84 using a strap connector
• CPC Class Codes: H01L 25/071 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/1033 : Gallium nitride [GaN]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13064 : High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package further includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of a common conductive leadframe with the common conductive leadframe electrically and mechanically coupling the control source with the sync drain. The common conductive leadframe thereby serves as the output terminal.

Claims

1. A method for manufacturing a stacked half-bridge package, said method comprising:

providing a control transistor having a control drain, a control source, and a control gate;

providing a sync transistor having a sync drain, a sync source, and a sync gate;

stacking said control and sync transistors on opposite sides of a common leadframe, said common leadframe serving as an output terminal by coupling said control source with said sync drain.

2. The method of claim 1, wherein said common leadframe comprises a web portion and a leg portion.

3. The method of claim 1, wherein respective bottom surfaces of said sync transistor and a leg portion of said common leadframe are substantially flush with one another.

4. The method of claim 1, further comprising connecting said control drain to a control drain leadframe by a conductive clip.

5. The method of claim 1, wherein said stacked half-bridge package further comprises a conductive clip including a web portion that is coupled to said control drain and including a leg portion that is coupled to a control drain leadframe.

6. The method of claim 1, further comprising coupling a conductive clip to said control drain at a topside of said stacked half-bridge package.

7. The method of claim 1, wherein said sync source comprises a solderable front metal (SFM).

8. The method of claim 1, wherein said sync source is exposed on a bottom surface of said sync transistor.

9. The method of claim 1, wherein said sync gate is exposed on a bottom surface of said sync transistor.

10. The method of claim 1, wherein said control transistor has top and bottom surfaces, said control drain being on said top surface and said control source and said control gate being on said bottom surface.

11. The method of claim 1, wherein said sync transistor has top and bottom surfaces, said sync drain being on said top surface and said sync source and said sync gate being on said bottom surface.

12. A method for manufacturing a stacked half-bridge package, said method comprising:

providing a control GaN HEMT having a control drain, a control source, and a control gate;

providing a sync GaN HEMT having a sync drain, a sync source, and a sync gate;

stacking said control and sync GaN HEMTs on opposite sides of a common leadframe, said common leadframe serving as an output terminal by coupling said control source with said sync drain.

13. The method of claim 12, wherein said common leadframe comprises a web portion and a leg portion.

14. The method of claim 12, wherein respective bottom surfaces of said sync GaN HEMT and a leg portion of said common leadframe are substantially flush with one another.

15. The method of claim 12, further comprising connecting said control drain to a control drain leadframe by a conductive clip.

16. The method of claim 12, wherein said stacked half-bridge package further comprises a conductive clip including a web portion that is coupled to said control drain and including a leg portion that is coupled to a control drain leadframe.

17. The method of claim 12, further comprising coupling a conductive clip to said control drain at a topside of said stacked half-bridge package.

18. The method of claim 12, wherein said sync source comprises a solderable front metal (SFM).

19. The method of claim 12, wherein said sync source is exposed on a bottom surface of said sync GaN HEMT.

20. The method of claim 12, wherein said sync gate is exposed on a bottom surface of said sync GaN HEMT.