Stacked half-bridge package
First Claim
1. A method for manufacturing a stacked half-bridge package, said method comprising:
- providing a control transistor having a control drain, a control source, and a control gate;
providing a sync transistor having a sync drain, a sync source, and a sync gate;
stacking said control and sync transistors on opposite sides of a common leadframe, said common leadframe serving as an output terminal by coupling said control source with said sync drain.
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Accused Products
Abstract
According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package further includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of a common conductive leadframe with the common conductive leadframe electrically and mechanically coupling the control source with the sync drain. The common conductive leadframe thereby serves as the output terminal.
41 Citations
20 Claims
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1. A method for manufacturing a stacked half-bridge package, said method comprising:
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providing a control transistor having a control drain, a control source, and a control gate; providing a sync transistor having a sync drain, a sync source, and a sync gate; stacking said control and sync transistors on opposite sides of a common leadframe, said common leadframe serving as an output terminal by coupling said control source with said sync drain. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method for manufacturing a stacked half-bridge package, said method comprising:
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providing a control GaN HEMT having a control drain, a control source, and a control gate; providing a sync GaN HEMT having a sync drain, a sync source, and a sync gate; stacking said control and sync GaN HEMTs on opposite sides of a common leadframe, said common leadframe serving as an output terminal by coupling said control source with said sync drain. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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Specification