Structure and method for advanced bulk fin isolation

• US 9,583,492 B2
• Filed: 03/14/2016
• Issued: 02/28/2017
• Est. Priority Date: 09/24/2014
• Status: Expired due to Fees

• Current Assignee: Elpis Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Doris, Bruce B., Khakifirooz, Ali, Lu, Darsen D., Reznicek, Alexander, Rim, Kern
• Primary Examiner(s): HOANG, QUOC DINH
• Application Number:
  US15/069,557
• Publication Number:
  US 20160197077A1
• Time in Patent Office: 351 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions

Abstract

A non-planar semiconductor structure containing semiconductor fins that are isolated from an underlying bulk silicon substrate by an epitaxial semiconductor stack is provided. The epitaxial semiconductor material stack that provides the isolation includes, from bottom to top, a semiconductor punch through stop containing at least one dopant of a conductivity type which differs from the conductivity type of the particular device region that the semiconductor fin is formed in, and a semiconductor diffusion barrier layer containing no n- or p-type dopant.

Claims

1. A method of forming a semiconductor structure, said method comprising:

providing a bulk silicon substrate comprising a device region for a p-type semiconductor device of a first conductivity type;

recessing an exposed portion of said bulk silicon substrate in said device region to expose a sub-surface of said bulk silicon substrate;

forming a semiconductor material stack of, from bottom to top, a semiconductor punch through stop layer containing at least one dopant of a second conductivity type which is opposite from said first conductivity type, a semiconductor diffusion barrier layer containing no n- or p-type dopant, and an epitaxial semiconductor layer on said sub-surface of said bulk silicon substrate; and

forming a plurality of semiconductor fins in said device region, wherein each semiconductor fin of said plurality of semiconductor fins comprises, from bottom to top, a remaining portion of said semiconductor punch through stop layer, a remaining portion of said semiconductor diffusion barrier, and a remaining portion of said epitaxial semiconductor layer, wherein said semiconductor punch through stop layer comprises a first carbon-doped silicon layer, said semiconductor diffusion barrier layer comprises a second carbon-doped silicon layer, and said epitaxial semiconductor layer comprises silicon or a silicon germanium alloy.

2. The method of claim 1, wherein said forming said semiconductor stack comprises epitaxially growing said semiconductor punch through stop layer over said sub-surface of said bulk silicon substrate, and epitaxially growing said semiconductor diffusion barrier layer over said semiconductor punch through stop layer.

3. The method of claim 1, further comprising another device region located adjacent to said device region for said semiconductor device of said first conductivity type, wherein said another device region is for another semiconductor device having said second conductivity type, and wherein a hard mask layer portion is present on said another device region during said recessing.

4. The method of claim 3, further comprising forming a dielectric spacer having a base located on said sub-surface of said bulk silicon substrate in said device region, wherein a topmost surface of said dielectric spacer is located between topmost surface of said hard mask layer portion and bottommost surface of said hard mask layer portion present on said another device region.

5. The method of claim 4, wherein a bottommost surface of said semiconductor punch through stop layer in said device region is coplanar with a bottommost surface of said dielectric spacer.

6. The method of claim 3, further comprising removing said hard mask layer portion in said another device region, after said recessing and prior to said forming said plurality of semiconductor fins in said device region, and forming a plurality of other semiconductor fins in said another device region simultaneously with said forming said plurality of semiconductor fins in said device region.

7. The method of claim 6, further comprising recessing said bulk silicon substrate in said another device region to expose another sub-surface of said bulk silicon substrate in said another device region, and forming another semiconductor material stack on said another sub-surface of said bulk silicon substrate in said another device region, said recessing of said bulk silicon substrate being performed subsequent to said removing of said hard mask layer and prior to forming of said plurality of semiconductor fins and said plurality of said other semiconductor fins.

8. The method of claim 7, wherein a topmost surface of said sub-surface of said bulk silicon substrate in said device region is coplanar with said topmost surface of said another sub-surface of said bulk silicon substrate in said another device region.

9. The method of claim 6, wherein each of said other semiconductor fins of said plurality of other semiconductor fins in said another device region comprises, from bottom to top, a first silicon germanium alloy portion containing at least one dopant of said first conductivity type, a second silicon germanium alloy portion containing no further dopant, and an epitaxial semiconductor portion.

10. The method of claim 6, wherein said dielectric spacer is removed during forming of said plurality of semiconductor fins in said device region and forming of said plurality of other semiconductor fins in said another device region.

11. The method of claim 10, wherein a recessed area is present in a remaining portion of said bulk silicon substrate, subsequent to said removal of said dielectric spacer.

12. The method of claim 3, wherein said plurality of other semiconductor fins comprises a silicon portion of said bulk silicon substrate.

13. A semiconductor structure comprising:

a bulk silicon substrate portion comprising a device region for a p-type semiconductor device of a first conductivity type; and

a plurality of semiconductor fins in said device region and extending upward from said bulk silicon substrate portion, wherein each semiconductor fin of said plurality of semiconductor fins comprises, from bottom to top, a semiconductor punch through stop portion containing a dopant of the second conductivity type that is opposite from said first conductivity type, a semiconductor diffusion barrier portion containing no n- or p-type dopant, and an epitaxial semiconductor portion, wherein said semiconductor punch through stop portion comprises a first carbon-doped silicon portion, said semiconductor diffusion barrier portion comprises a second carbon-doped silicon portion, and said epitaxial semiconductor portion comprises silicon or a silicon germanium alloy.

14. The semiconductor structure of claim 13, further comprising another device region located adjacent to said device region for said semiconductor device of said first conductivity type, wherein said another device region is for another semiconductor device having said second conductivity type.

15. The semiconductor structure of claim 14, further comprising a plurality of other semiconductor fins in said another device region, wherein each semiconductor fin of said plurality of other semiconductor fins comprises a silicon portion in direct physical contact with topmost surface of said bulk silicon substrate portion.

16. The semiconductor structure of claim 14, further comprising a functional gate structure straddling over a portion of each semiconductor fin of said plurality of semiconductor fins, and straddling over a portion of said plurality of other semiconductor fins.

17. The semiconductor structure of claim 14, wherein topmost surface of each semiconductor fin of said plurality of semiconductor fins is coplanar with a topmost surface each semiconductor fin of said plurality of other semiconductor fins.

18. The semiconductor structure of claim 14, wherein a topmost surface of said sub-surface of said bulk silicon substrate in said device region is coplanar with said topmost surface of an another sub-surface of said bulk silicon substrate in said another device region.