Method for manufacturing injection-enhanced insulated-gate bipolar transistor
First Claim
1. A method of manufacturing an injection enhanced IGBT (Insulated Gate Bipolar Transistor), comprising steps as follow:
- providing an N-type substrate;
forming a P-type doped layer on the N-type substrate;
forming a hard layer on the P-type doped layer;
etching the hard layer to form a hard layer having a trench pattern;
etching the P-type doped layer to form a trench extending into the N-type substrate;
forming an N-type doped layer on a sidewall and a bottom of the trench;
removing the hard layer having the trench pattern;
performing a drive-in to the P-type dopant of the P-type doped layer and the N-type dopant of the N-type doped layer together, the P-type dopant forming a P-type base region by diffusing, and the N-type dopant forming an N-type buffer layer by diffusing;
forming a gate oxide dielectric layer on a surface of the trench; and
depositing a polysilicon layer in the trench on which the gate oxide dielectric layer is formed.
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Accused Products
Abstract
A method for manufacturing an injection-enhanced insulated-gate bipolar transistor, comprising the following steps: an n-type substrate (12) is provided; a p-type doped layer (14) is formed on the n-type substrate (12); a hard layer (20) is formed on the p-type doped layer (14); a groove (40) extending to the n-type substrate (12) is formed by etching on the p-type doped layer (14); an n-type doped layer (50) is formed on the sidewalls and bottom of the groove (40); the hard layer (20) is removed; p-type impurities of the p-type doped layer (14) and n-type impurities of the n-type doped layer (50) are driven in together, where the p-type impurities are diffused to form a p-type base region (60), and the n-type impurities are diffused to form an n-type buffer layer (70); a gated oxide dielectric layer (80) is formed on the surface of the groove (40); and, a polysilicon layer (90) is deposited in the groove having formed therein the gate oxide dielectric layer (80). In the method for manufacturing the injection-enhanced insulated-gate bipolar transistor, the p-type doped layer (14) and the n-type doped layer (50) are driven in together to form the p-type base region (60) and the n-type buffer layer (70), as only one drive-in process is required, production cycle is shortened in comparison with a conventional method for manufacturing the injection-enhanced insulated-gate bipolar transistor.
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Citations
10 Claims
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1. A method of manufacturing an injection enhanced IGBT (Insulated Gate Bipolar Transistor), comprising steps as follow:
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providing an N-type substrate; forming a P-type doped layer on the N-type substrate; forming a hard layer on the P-type doped layer; etching the hard layer to form a hard layer having a trench pattern; etching the P-type doped layer to form a trench extending into the N-type substrate; forming an N-type doped layer on a sidewall and a bottom of the trench; removing the hard layer having the trench pattern; performing a drive-in to the P-type dopant of the P-type doped layer and the N-type dopant of the N-type doped layer together, the P-type dopant forming a P-type base region by diffusing, and the N-type dopant forming an N-type buffer layer by diffusing; forming a gate oxide dielectric layer on a surface of the trench; and depositing a polysilicon layer in the trench on which the gate oxide dielectric layer is formed. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method of manufacturing the injection-enhanced IGBT, comprising steps as follow:
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providing an N-type substrate; forming a hard layer on the N-type doped layer; etching the hard layer to form a hard layer having a trench pattern; etching the N-type doped layer to form a trench; forming an N-type doped layer on a sidewall and a bottom of the trench; removing the hard layer having the trench pattern; forming a mask layer in the trench, the mask layer filling the trench; forming a P-type doped layer on a surface of the N-type substrate which forms the trench; removing the mask layer; performing a drive-in to the P-type dopant of the P-type doped layer and the N-type dopant of the N-type doped layer together, the P-type dopant forming a P-type base region by diffusing, and the N-type dopant forming an N-type buffer layer by diffusing; forming a gate oxide dielectric layer on a surface of the trench; and depositing a polysilicon layer in the trench on which the gate oxide dielectric layer is formed.
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Specification
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- Resources
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Current AssigneeCSMC Technologies FAB1 Company Limited (CSMC Manufacturing Company Limited)
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Original AssigneeCSMC Technologies FAB1 Company Limited (CSMC Manufacturing Company Limited)
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InventorsWang, Wanli, Deng, Xiaoshe, Wang, Genyi, Huang, Xuan
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Primary Examiner(s)Manno, Jessica
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Assistant Examiner(s)Maruf, Sheikh
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Application NumberUS14/902,220Publication NumberTime in Patent Office951 DaysField of Search438/138, 438/139, 438/270, 438/543, 257/139, 257/330, 257107-109, 257/655, 257/140, 257/133, 257/E21.383, 257/E21.384, 257/E21.389US Class Current1/1CPC Class CodesH01L 21/2253 by ion implantationH01L 21/26513 of electrically active speciesH01L 21/266 using masks H01L21/26586 ta...H01L 21/324 Thermal treatment for modif...H01L 29/063 Reduced surface field [RESU...H01L 29/1095 Body region, i.e. base regi...H01L 29/66348 with a recessed gateH01L 29/7397 and a gate structure lying ...
