Trench MOSFET having reduced gate charge

• US 9,583,611 B2
• Filed: 03/14/2016
• Issued: 02/28/2017
• Est. Priority Date: 05/30/2014
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Grebs, Thomas Eugene, Rahman, Touhidur, Kocon, Christopher Boguslaw
• Primary Examiner(s): Nicely, Joseph C
• Application Number:
  US15/069,038
• Publication Number:
  US 20160197177A1
• Time in Patent Office: 351 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/0882 Disposition
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66356 Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
• CPC Class Codes: H01L 29/7391 Gated diode structures
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7804 the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7805 in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/861 Diodes

Abstract

A trench MOSFET device includes a semiconductor layer of a first doping type. MOS transistor cells are in a body region of a second doping type in the semiconductor layer. The transistor cells include a first cell type including a first trench providing a first gate electrode or the first gate electrode is on the semiconductor surface between the first trench and a second trench, and a first source region is formed in the body region. The first gate electrode is electrically isolated from the first source region. A second cell type has a third trench providing a second gate electrode or the second gate electrode is on the semiconductor surface between the third trench and a fourth trench, and a second source region is in the body region. An electrically conductive member directly connects the second gate electrode, first source region and second source region together.

Claims

1. A transistor device, comprising:

a drain region;

a source region positioned above the drain region;

an active transistor cell including a first gate electrode isolated from a portion of the source region adjacent to the first gate electrode; and

a diode connected transistor cell positioned adjacent to the active transistor cell, the diode connected transistor cell including a second gate electrode coupled to the source region.

2. The transistor device of claim 1, further comprising:

a source metal layer formed above the first and second gate electrodes, the source metal layer connected to the source region;

a dielectric layer isolating the first gate electrode from the source metal layer and the source region; and

a gate contact structure penetrating the dielectric layer and connecting the second gate electrode to the source metal layer.

3. The transistor device of claim 1, further comprising:

a body region positioned between the drain region and the source region;

a trench penetrating the source region and the body region, the trench positioned between the active transistor cell and the diode connected transistor cell; and

a body contact structure occupying the trench to couple the source region with the body region.

4. The transistor device of claim 1, further comprising:

a body region positioned between the drain region and the source region;

a gate trench positioned within the active transistor cell, the gate trench penetrating the source region and the body region, and housing the first gate electrode; and

a gate dielectric liner lining the gate trench and isolating the first gate electrode from the source region and the body region along a sidewall of the gate trench.

5. The transistor device of claim 1, further comprising:

a body region positioned between the drain region and the source region;

a gate trench positioned within the diode connected transistor cell, the gate trench penetrating the source region and the body region, and housing the second gate electrode; and

a gate dielectric liner lining the gate trench and isolating the second gate electrode from the source region and the body region along a sidewall of the gate trench.

6. The transistor device of claim 1, wherein the portion of the source region is symmetrically positioned around the first gate electrode.

7. The transistor device of claim 1, wherein the portion of the source region is positioned under the first gate electrode.

8. The transistor device of claim 1, further comprising:

a drain drift region positioned between the drain region and the source region.

9. The transistor device of claim 1, wherein the active transistor cell includes a first and second active transistor cells positioned symmetrically around the diode connected transistor cell.

10. The transistor device of claim 1, wherein:

the active transistor cell includes N active transistor cells positioned laterally around the diode connected transistor cell; and

N is a positive integer ranges from 3 to 10.

11. A transistor device, comprising:

a drain layer;

a source layer positioned above the drain layer and having a first source region and a second source region separated from the first source region;

a source metal layer positioned above the source layer and electrically coupling the first source region to the second source region;

a first transistor cell overlapping the first source region, the first transistor cell including a first gate electrode free from being directly connected to the first source region; and

a second transistor cell overlapping the second source region, the second transistor cell including a second gate electrode coupled to the second source region via the source metal layer.

12. The transistor device of claim 11, further comprising:

a dielectric layer separating the first gate electrode from the source metal layer and the first source region; and

a gate contact structure penetrating the dielectric layer and connecting the second gate electrode to the source metal layer.

13. The transistor device of claim 11, further comprising:

a body region positioned between the drain layer and the source layer;

a gate trench positioned within the first transistor cell, the gate trench penetrating the first source region and the body region, and housing the first gate electrode; and

a gate dielectric liner lining the gate trench and isolating the first gate electrode from the first source region and the body region along a sidewall of the gate trench.

14. The transistor device of claim 11, further comprising:

a body region positioned between the drain layer and the source layer;

a gate trench positioned within the second transistor cell, the gate trench penetrating the second source region and the body region, and housing the second gate electrode; and

a gate dielectric liner lining the gate trench and isolating the second gate electrode from the second source region and the body region along a sidewall of the gate trench.

15. The transistor device of claim 11, wherein the first source region is symmetrically positioned around the first gate electrode.

16. The transistor device of claim 11, wherein the first source region is positioned under the first gate electrode.

17. The transistor device of claim 11, wherein:

the first transistor cell includes N active transistor cells positioned laterally around the second transistor cell; and

N is a positive integer ranges from 3 to 10.

18. An integrated circuit, comprising:

trench MOSFET devices, each having;

a drain layer;

a source layer positioned above the drain layer and having a first source region and a second source region separated from the first source region;

a source metal layer positioned above the source layer and electrically coupling the first source region to the second source region;

a first transistor cell overlapping the first source region, the first transistor cell including a first gate electrode free from being directly connected to the first source region; and

a second transistor cell overlapping the second source region, the second transistor cell including a second gate electrode coupled to the second source region via the source metal layer.

19. The integrated circuit of claim 18, wherein each of the trench MOSFET devices includes:

a dielectric layer separating the first gate electrode from the source metal layer and the first source region; and

a gate contact structure penetrating the dielectric layer and connecting the second gate electrode to the source metal layer.

20. The integrated circuit of claim 18, wherein each of the trench MOSFET devices includes:

a body region positioned between the drain layer and the source layer;

a gate trench positioned within the second transistor cell, the gate trench penetrating the second source region and the body region, and housing the second gate electrode; and

a gate dielectric liner lining the gate trench and isolating the second gate electrode from the second source region and the body region along a sidewall of the gate trench.