Semiconductor device with a low-K spacer and method of forming the same
First Claim
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1. A device, comprising:
- a semiconductor substrate;
a gate stack on the semiconductor substrate, the gate stack including a gate conductor layer and a gate dielectric layer under the gate conductor directly on the semiconductor substrate and on sidewalls of the gate conductor layer;
low-k spacers adjacent to the gate dielectric layer;
raised source/drain (RSD) regions adjacent to the low-k spacers;
an ILD layer on the RSD regions and the low-k spacers, wherein the ILD layer overhangs the low-k spacers; and
spacers between the gate dielectric layer and the low-k spacers and between the ILD layer and the gate dielectric layer above the low-k spacers.
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Abstract
A device includes a semiconductor substrate. A gate stack on the semiconductor substrate includes a gate dielectric layer and a gate conductor layer. Low-k spacers are adjacent to the gate dielectric layer. Raised source/drain (RSD) regions are adjacent to the low-k spacers. The low-k spacers are embedded in an ILD on the RSD regions.
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Citations
18 Claims
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1. A device, comprising:
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a semiconductor substrate; a gate stack on the semiconductor substrate, the gate stack including a gate conductor layer and a gate dielectric layer under the gate conductor directly on the semiconductor substrate and on sidewalls of the gate conductor layer; low-k spacers adjacent to the gate dielectric layer; raised source/drain (RSD) regions adjacent to the low-k spacers; an ILD layer on the RSD regions and the low-k spacers, wherein the ILD layer overhangs the low-k spacers; and spacers between the gate dielectric layer and the low-k spacers and between the ILD layer and the gate dielectric layer above the low-k spacers. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method in a computer-aided design system for generating a functional design model of a semiconductor device, the method comprising:
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generating a functional representation of a gate stack on the semiconductor substrate, the gate stack including a gate conductor layer and a gate dielectric layer under the gate conductor directly on the semiconductor substrate and on sidewalls of the gate conductor layer; generating a functional representation of low-k spacers adjacent to the gate dielectric layer; generating a functional representation of raised source/drain (RSD) regions adjacent to the low-k spacers; generating a functional representation of an ILD layer on the RSD regions and the low-k spacers, wherein the ILD layer overhangs the low-k spacers; generating a functional representation of spacers between the gate dielectric layer and the low-k spacers and between the ILD layer and the gate dielectric layer above the low-k spacers and manufacturing the semiconductor device using the generated functional representations. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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Specification