Semiconductor device with a low-K spacer and method of forming the same

• US 9,583,628 B2
• Filed: 12/03/2014
• Issued: 02/28/2017
• Est. Priority Date: 01/20/2012
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Cheng, Kangguo, Doris, Bruce B., Khakifirooz, Ali, La Tulipe, Douglas C. Jr.
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): Parker, John M
• Application Number:
  US14/558,904
• Publication Number:
  US 20150137240A1
• Time in Patent Office: 818 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/772 Field effect transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors

Abstract

A device includes a semiconductor substrate. A gate stack on the semiconductor substrate includes a gate dielectric layer and a gate conductor layer. Low-k spacers are adjacent to the gate dielectric layer. Raised source/drain (RSD) regions are adjacent to the low-k spacers. The low-k spacers are embedded in an ILD on the RSD regions.

Claims

1. A device, comprising:

a semiconductor substrate;

a gate stack on the semiconductor substrate, the gate stack including a gate conductor layer and a gate dielectric layer under the gate conductor directly on the semiconductor substrate and on sidewalls of the gate conductor layer;

low-k spacers adjacent to the gate dielectric layer;

raised source/drain (RSD) regions adjacent to the low-k spacers;

an ILD layer on the RSD regions and the low-k spacers, wherein the ILD layer overhangs the low-k spacers; and

spacers between the gate dielectric layer and the low-k spacers and between the ILD layer and the gate dielectric layer above the low-k spacers.

2. The device according to claim 1, wherein the semiconductor substrate comprises a semiconductor-on-insulator (SOI) substrate having an ETSOI layer, a BOX layer and a substrate layer.

3. The device according to claim 2, wherein the ETSOI layer has a thickness in a range from about 3 nm to about 10 nm.

4. The device according to claim 1, wherein the gate dielectric layer comprises a high-k material.

5. The device according to claim 4, wherein the high-k material is selected from the group consisting of hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide and lead zinc niobate.

6. The device according to claim 1, wherein the gate conductor layer comprises a metal.

7. The device according to claim 6, wherein the metal is selected from the group consisting of:

tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminum, lead, platinum, tin, silver and gold.

8. The device according to claim 1, wherein the spacers are thin nitride spacers having a width in a range from about 2 nm to about 6 nm.

9. The structure of claim 1, wherein the wherein the ILD layer overhangs the low-k spacers, directly contacting an upper portion of the low-k spacers and the spacers above the low-k spacers.

10. A method in a computer-aided design system for generating a functional design model of a semiconductor device, the method comprising:

generating a functional representation of a gate stack on the semiconductor substrate, the gate stack including a gate conductor layer and a gate dielectric layer under the gate conductor directly on the semiconductor substrate and on sidewalls of the gate conductor layer;

generating a functional representation of low-k spacers adjacent to the gate dielectric layer;

generating a functional representation of raised source/drain (RSD) regions adjacent to the low-k spacers;

generating a functional representation of an ILD layer on the RSD regions and the low-k spacers, wherein the ILD layer overhangs the low-k spacers;

generating a functional representation of spacers between the gate dielectric layer and the low-k spacers and between the ILD layer and the gate dielectric layer above the low-k spacers and

manufacturing the semiconductor device using the generated functional representations.

11. The method according to claim 10, wherein the semiconductor substrate comprises a semiconductor-on-insulator (SOI) substrate having an ETSOI layer, a BOX layer and a substrate layer.

12. The method according to claim 11, wherein the ETSOI layer has a thickness in a range from about 3 nm to about 10 nm.

13. The method according to claim 10, wherein the gate dielectric layer comprises a high-k material.

14. The method according to claim 13, wherein the high-k material is selected from the group consisting of:

hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide and lead zinc niobate.

15. The method according to claim 10, wherein the gate conductor layer comprises a metal.

16. The method according to claim 15, wherein the metal is selected from the group consisting of:

tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminum, lead, platinum, tin, silver and gold.

17. The method according to claim 10, wherein the functional design model is synthesized into a netlist.

18. The method according to claim 10, wherein the spacers are nitride spacers having a width in a range from about 2 nm to about 6 nm.