Low warpage wafer bonding through use of slotted substrates

• US 9,583,676 B2
• Filed: 10/05/2012
• Issued: 02/28/2017
• Est. Priority Date: 10/21/2011
• Status: Active Grant

• Current Assignee: Lumileds LLC (Apollo Global Management, Inc.)
• Original Assignee: Koninklijke Philips N.V.
• Inventors: Engelen, Roy Antoin Bastiaan, De Samber, Marc Andre, Van Grunsven, Eric Cornelis Egbertus
• Primary Examiner(s): Rizkallah, Kimberly
• Assistant Examiner(s): Turner, Brian
• Application Number:
  US14/352,698
• Publication Number:
  US 20140252405A1
• Time in Patent Office: 1,607 Days
• Field of Search: 257/99, 257/79, 257/622, 257/E33.001, 438/22, 438/28, 438/107
• US Class Current: 1/1
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 2933/0066 relating to arrangements for conducting electric current to or from the semiconductor body
• CPC Class Codes: H01L 33/0054 for devices with an active region comprising only group IV elements
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/0095 Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01L 33/12 with a stress relaxation structure, e.g. buffer layer
• CPC Class Codes: H01L 33/486 adapted for surface mounting
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

In a wafer bonding process, one or both of two wafer substrates are scored prior to bonding. By creating slots in the substrate, the wafer'"'"'s characteristics during bonding are similar to that of a thinner wafer, thereby reducing potential warpage due to differences in CTE characteristics associated with each of the wafers. Preferably, the slots are created consistent with the singulation/dicing pattern, so that the slots will not be present in the singulated packages, thereby retaining the structural characteristics of the full-thickness substrates.

Claims

1. A structure comprising:

a first semiconductor wafer comprising a plurality of semiconductor devices, wherein the first semiconductor wafer comprises an insulating growth substrate, wherein the plurality of semiconductor devices each comprise a semiconductor structure disposed on the insulating growth substrate, and

a second wafer that is bonded to the first wafer via bonding surfaces on the first and second wafers,

wherein, to reduce warpage of the structure, the second wafer is scored with a plurality of slots on a surface that is opposite to the bonding surface.

2. The structure of claim 1, wherein the semiconductor devices include light emitting devices.

3. The structure of claim 1, wherein the slots are aligned with boundaries between the semiconductor devices.

4. The structure of claim 1, wherein the second wafer has a thickness T, and the slots have a depth D that is between forty and eighty percent of the thickness T.

5. The structure of claim 1, wherein the semiconductor devices have a device width, and the slots have a slot width that is between five and twenty percent of the device width.

6. The structure of claim 1, wherein the second wafer comprises a plurality of through-holes that extend through an entire thickness of the second wafer.

7. The structure of claim 6, wherein:

the through-holes are aligned with contact areas on the plurality of semiconductor devices; and

conductors are disposed in the through-holes.

8. The structure of claim 1, wherein neighboring slots are disposed an integer number of semiconductor devices apart.

9. The device of claim 1 wherein:

the bonding surface on the first semiconductor wafer comprises a surface of the plurality of semiconductor devices.

10. A method comprising:

growing a semiconductor structure on a growth substrate, wherein the growth substrate is insulating;

creating a plurality of semiconductor devices on the growth substrate, the growth substrate and the plurality of semiconductor devices forming a first wafer, and

bonding the first wafer to a second wafer that includes a submount substrate via bonding surfaces of the first and second wafers,

to reduce warpage of the structure, the submount substrate is scored with a plurality of slots on a surface that is opposite to the bonding surface of the wafer.

11. The method of claim 10, wherein the plurality of slots are aligned with boundaries between the semiconductor devices.

12. The method of claim 10, wherein the semiconductor devices include light emitting devices.

13. The method of claim 10, wherein the submount substrate has a thickness T, and the slots have a depth D that is between forty and eighty percent of the thickness T.

14. The method of claim 10, wherein the semiconductor devices have a device width, and the slots have a slot width that is between five and twenty percent of the device width.

15. The method of claim 10, wherein the growth substrate includes sapphire, and the submount substrate includes silicon.

16. The method of claim 10, wherein the second wafer comprises a plurality of through-holes that extend through an entire thickness of the submount substrate.

17. The method of claim 16, wherein:

the through-holes are aligned with contact areas on the plurality of semiconductor devices; and

conductors are disposed in the through-holes.

18. The method of claim 10, wherein neighboring slots are disposed an integer number of semiconductor devices apart.

19. The method of claim 10 wherein the bonding surface of the first wafer comprises a surface of the plurality of semiconductor devices, the method further comprising after said bonding the first wafer to a second wafer, removing the growth substrate from the plurality of semiconductor devices.