Rapid transition schmitt trigger circuit

• US 9,584,101 B2
• Filed: 06/15/2015
• Issued: 02/28/2017
• Est. Priority Date: 12/17/2012
• Status: Active Grant

• Current Assignee: Smarter Microelectronics (Guangzhou) Co.,Ltd
• Original Assignee: Smarter Microelectronics (Guangzhou) Co.,Ltd
• Inventors: Li, Yang
• Primary Examiner(s): Nguyen, Hai L
• Application Number:
  US14/739,482
• Publication Number:
  US 20150280694A1
• Time in Patent Office: 624 Days
• US Class Current: 1/1
• CPC Class Codes: H03K 3/3565 Bistables with hysteresis, e.g. Schmitt trigger

Abstract

A small-sized rapid transition Schmitt trigger circuit for use with a silicon-on-insulator process includes: a first NMOS transistor, a first PMOS transistor, a second NMOS transistor, a second PMOS transistor, and a PMOS/NMOS body control circuit; wherein, the PMOS/NMOS body control circuit is configured to, through changing threshold voltages of the first NMOS transistor and the first PMOS transistor, enable different flip-flop threshold voltages for input transitions from high electrical levels to low electrical levels and from low electrical levels to high electrical levels.

Claims

1. A small-sized rapid transition Schmitt trigger circuit for use with a silicon-on-insulator process, comprising:

a first NMOS transistor, a first PMOS transistor, a second NMOS transistor, a second PMOS transistor, and a PMOS/NMOS body control circuit;

wherein, the PMOS/NMOS body control circuit comprises a plurality transistors connected such that, through turning on and off the plurality of transistors thereby changing threshold voltages of the first NMOS transistor and the first PMOS transistor, enables different flip-flop threshold voltages for input transitions from high electrical levels to low electrical levels and from low electrical levels to high electrical levels;

wherein the PMOS/NMOS body control circuit is further configured to, through controlling voltages of body regions of the first NMOS transistor and the first PMOS transistor, enable the different flip-flop threshold voltages for the input transitions from high electrical levels to low electrical levels and from low electrical levels to high electrical levels; and

wherein the PMOS/NMOS body control circuit is further configured to;

if an input of the Schmitt trigger circuit is at a low electrical level, set a voltage of the body region of the first NMOS transistor to 0, and set a voltage of the body region of the first PMOS transistor to V_D1;

if the input of the Schmitt trigger circuit is at a high electrical level, set the voltage of the body region of the first NMOS transistor to V_D2, and set the voltage of the body region of the first PMOS transistor to V_DD;

wherein, V_DD represents a power supply voltage, V_D1 represents a low voltage outputted by a first output end of the PMOS/NMOS body control circuit, said first output end is connected to the body region of the first PMOS transistor;

V_D2 represents a high voltage outputted by a second output end of the PMOS/NMOS transistor body control circuit, said second output end is connected to the body region of the first NMOS transistor.

2. The circuit of claim 1, wherein a gate electrode of the first PMOS transistor is connected to an input end, a source electrode of the first PMOS transistor is connected to a power supply, a drain electrode of the first PMOS transistor is connected to an inter-stage common node;

a gate electrode of the second PMOS transistor is connected to the inter-stage common node, the source electrode of the second transistor is connected to the power supply, the drain electrode of the second PMOS transistor is connected to an output end.

3. The circuit of claim 2, wherein a gate electrode of the first NMOS transistor is connected to the input end, a source electrode of the first NMOS transistor is connected to a ground, a drain electrode of the first NMOS transistor is connected to the inter-stage common node;

a gate electrode of the second NMOS transistor is connected to the inter-stage common node, a source electrode of the second NMOS transistor is connected to the ground, a drain electrode of the second NMOS transistor is connected to the output end.

4. The circuit of claim 1, wherein said PMOS/NMOS body control circuit comprises:

a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first diode, a resistor, and a second diode.

5. The circuit of claim 4, wherein, a drain electrode of the third PMOS transistor and a source electrode of the fourth PMOS transistor are connected to the body region of the first PMOS transistor;

a drain electrode of the fourth NMOS and a source electrode of the third NMOS transistor are connected to the body region of the first NMOS transistor;

a gate electrode of the third NMOS transistor is connected to a gate electrode of the fourth PMOS transistor and an output end;

a gate electrode of the fourth NMOS transistor is connected to a gate electrode of the third PMOS transistor;

a source electrode of the fourth NMOS transistor is connected to the ground, a source electrode of the third PMOS transistor is connected to the power supply;

a cathode of the first diode is connected to the power supply, an anode of the first diode is connected to one end of the resistor and a drain electrode of the fourth PMOS transistor;

an anode of the second diode is connected to the ground, a cathode of the second diode is connected to another end of the resistor and a drain electrode of the third NMOS transistor.

6. An silicon-on-insulator-based integrated circuit comprising one or more waveform shaping circuits including a rapid transition Schmitt trigger circuit, the Schmitt trigger circuit including:

a first NMOS transistor, a first PMOS transistor, a second NMOS transistor, a second PMOS transistor, and a PMOS/NMOS body control circuit;

wherein, the PMOS/NMOS body control circuit comprises a plurality transistors connected such that, through turning on and off the plurality of transistors thereby changing threshold voltages of the first NMOS transistor and the first PMOS transistor, enables different flip-flop threshold voltages for input transitions from high electrical levels to low electrical levels and from low electrical levels to high electrical levels;

wherein the PMOS/NMOS body control circuit is further configured to, through controlling voltages of body regions of the first NMOS transistor and the first PMOS transistor, enable the different flip-flop threshold voltages for the input transitions from high electrical levels to low electrical levels and from low electrical levels to high electrical levels; and

wherein the PMOS/NMOS body control circuit is further configured to;

if an input of the Schmitt trigger circuit is at a low electrical level, set a voltage of the body region of the first NMOS transistor to 0, and set a voltage of the body region of the first PMOS transistor to V_D1;

if the input of the Schmitt trigger circuit is at a high electrical level, set the voltage of the body region of the first NMOS transistor to V_D2, and set the voltage of the body region of the first PMOS transistor to V_DD;

wherein, V_DD represents a power supply voltage, V_D1 represents a low voltage outputted by a first output end of the PMOS/NMOS body control circuit, said first output end is connected to the body region of the first PMOS transistor;

V_D2 represents a high voltage outputted by a second output end of the PMOS/NMOS transistor body control circuit, said second output end is connected to the body region of the first NMOS transistor.

7. The integrated circuit of claim 6, wherein a gate electrode of the first PMOS transistor is connected to an input end, a source electrode of the first PMOS transistor is connected to a power supply, a drain electrode of the first PMOS transistor is connected to an inter-stage common node;

a gate electrode of the second PMOS transistor is connected to the inter-stage common node, the source electrode of the second transistor is connected to the power supply, a drain electrode of the second PMOS transistor is connected to an output end.

8. The integrated circuit of claim 7, wherein, a gate electrode of the first NMOS transistor is connected to the input end, a source electrode of the first NMOS transistor is connected to the ground, a drain electrode of the first NMOS transistor is connected to the inter-stage common node;

a gate electrode of the second NMOS transistor is connected to the inter-stage common node, a source electrode of the second NMOS transistor is connected to the ground, a drain electrode of the second NMOS transistor is connected to the output end.

9. The integrated circuit of claim 6, wherein said PMOS/NMOS body control circuit comprises:

a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first diode, a resistor and a second diode.

10. The integrated circuit of claim 9, wherein a drain electrode of the third PMOS transistor and a source electrode of the fourth PMOS transistor are connected to a body region of the first PMOS transistor;

a drain electrode of the fourth NMOS and a source electrode of the third NMOS transistor are connected to a body region of the first NMOS transistor;

a gate electrode of the third NMOS transistor is connected to the gate electrode of the fourth PMOS transistor and an output end;

a gate electrode of the fourth NMOS transistor is connected to a gate electrode of the third PMOS transistor;

a source electrode of the fourth NMOS transistor is connected to the ground, a source electrode of the third PMOS transistor is connected to the power supply;

a cathode of the first diode is connected to the power supply, an anode of the first diode is connected to one end of the resistor and a drain electrode of the fourth PMOS transistor;

an anode of the second diode is connected to the ground, a cathode of the second diode is connected to another end of the resistor and a drain electrode of the third NMOS transistor.

11. A method of realizing, in a silicon-on-insulator-based integrated circuit, a rapid transition with a Schmitt trigger circuit, wherein the Schmitt trigger circuit includes:

a first NMOS transistor, a first PMOS transistor, a second NMOS transistor, a second PMOS transistor, and a PMOS/NMOS body control circuit comprising a plurality of inter-connected transistors electrically coupled with the first NMOS transistor and the first PMOS transistor;

the method comprising;

configuring the PMOS/NMOS body control circuit to, through turning on and off the plurality of transistors thereby changing threshold voltages of the first NMOS transistor and the first PMOS transistor, enable different flip-flop threshold voltages for input transitions from high electrical levels to low electrical levels and from low electrical levels to high electrical levels;

wherein the PMOS/NMOS body control circuit is further configured to, through controlling voltages of body regions of the first NMOS transistor and the first PMOS transistor, enable the different flip-flop threshold voltages for the input transitions from high electrical levels to low electrical levels and from low electrical levels to high electrical levels; and

wherein the PMOS/NMOS body control circuit is further configured to;

if an input of the Schmitt trigger circuit is at a low electrical level, set a voltage of the body region of the first NMOS transistor to 0, and set a voltage of the body region of the first PMOS transistor to V_D1;

if the input of the Schmitt trigger circuit is at a high electrical level, set the voltage of the body region of the first NMOS transistor to V_D2, and set the voltage of the body region of the first PMOS transistor to V_DD;

wherein, V_DD represents a power supply voltage, V_D1 represents a low voltage outputted by a first output end of the PMOS/NMOS body control circuit, said first output end is connected to the body region of the first PMOS transistor;

V_D2 represents a high voltage outputted by a second output end of the PMOS/NMOS transistor body control circuit, said second output end is connected to the body region of the first NMOS transistor.

12. The method of claim 11, wherein a gate electrode of the first PMOS transistor is connected to an input end, a source electrode of the first PMOS transistor is connected to a power supply, a drain electrode of the first PMOS transistor is connected to an inter-stage common node;

a gate electrode of the second PMOS transistor is connected to the inter-stage common node, the source electrode of the second transistor is connected to the power supply, the drain electrode of the second PMOS transistor is connected to an output end.

13. The method of claim 12, wherein a gate electrode of the first NMOS transistor is connected to the input end, a source electrode of the first NMOS transistor is connected to the ground, a drain electrode of the first transistor is connected to the inter-stage common node;

a gate electrode of the second NMOS transistor is connected to the inter-stage common node, a source electrode of the second NMOS transistor is connected to the ground, a drain electrode of the second NMOS transistor is connected to the output end.

14. The method of claim 11, wherein said PMOS/NMOS body control circuit comprises:

a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first diode, a resistor and a second diode; and

wherein a drain electrode of the third PMOS transistor and a source electrode of the fourth PMOS transistor are connected to the body region of the first PMOS transistor;

a drain electrode of the fourth NMOS and a source electrode of the third NMOS transistor are connected to the body region of the first NMOS transistor;

a gate electrode of the third NMOS transistor is connected to the gate electrode of the fourth PMOS transistor and an output end;

a gate electrode of the fourth NMOS transistor is connected to a gate electrode of the third PMOS transistor;

a source electrode of the fourth NMOS transistor is connected to the ground, a source electrode of the third PMOS transistor is connected to the power supply;

a cathode of the first diode is connected to the power supply, an anode of the first diode is connected to one end of the resistor and a drain electrode of the fourth PMOS transistor;

an anode of the second diode is connected to the ground, a cathode of the second diode is connected to another end of the resistor and a drain electrode of the third NMOS transistor.