Radio frequency transceiver loopback testing

• US 9,584,175 B2
• Filed: 12/16/2014
• Issued: 02/28/2017
• Est. Priority Date: 12/16/2014
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Inventors: Vogler, Jayson D., Waheed, Khurram, Stoll, Chris N.
• Primary Examiner(s): Bolourchi, Nader
• Application Number:
  US14/572,295
• Publication Number:
  US 20160174094A1
• Time in Patent Office: 805 Days
• Field of Search: 455/423
• US Class Current: 1/1
• CPC Class Codes: H04B 1/40 Circuits
• CPC Class Codes: H04B 17/14 of the whole transmission and reception path, e.g. self-test loop-back
• CPC Class Codes: H04B 17/18 Monitoring during normal operation
• CPC Class Codes: H04W 24/10 Scheduling measurement reports ; Arrangements for measurement reports

Abstract

An integrated circuit includes a receiver portion, a transmitter portion, and a modulated phase locked loop. The receiver portion is for receiving a radio frequency (RF) signal at a receiver input of the receiver portion. The transmitter portion is for transmitting an RF signal at a transmitter output of the transmitter portion. The modulated phase locked loop (PLL) is shared between the receiver portion and the transmitter portion. The transmitter output and receiver input are coupled together in a loopback configuration during a test mode. The transmitter portion and the receiver portion are enabled concurrently while a modulated PLL signal is provided to the receiver portion from the transmitter portion via the loopback configuration.

Claims

1. An integrated circuit comprising:

a receiver portion comprising;

a first receiver input to receive a radio frequency (RF) signal;

a second receiver input to receive an output signal from a phase locked loop; and

a mixer coupled to the first receiver input and to the second receiver input;

a transmitter portion to transmit an RF signal at a transmitter output of the transmitter portion and to receive a modulated PLL signal at a transmitter input of the transmitter portion;

the phase locked loop (PLL) shared between the receiver portion and the transmitter portion, the PLL during normal operation being used by the transmitter portion during a transmit mode and being used by the receiver portion during a receive mode, and the PLL providing at an output the modulated PLL signal based on a transmitter modulation signal; and

wherein, during a test mode, the transmitter output and the first receiver input are coupled together in a loopback configuration, and the modulated PLL signal is provided to both the first receiver input and to the second receiver input.

2. The integrated circuit of claim 1, further comprising a common RF port whereby the transmitter output and the first receiver input are coupled in the loopback configuration during the test mode.

3. The integrated circuit of claim 1, wherein the transmitter portion and the receiver portion are simultaneously operable.

4. The integrated circuit of claim 1, wherein the PLL is configured to provide a predetermined constant envelope modulation to the transmitter portion and to the second receiver input of receiver portion.

5. The integrated circuit of claim 1, further comprising a memory for storing at least a portion of a digitized baseband signal representative of the RF signal received at the first receiver input.

6. The integrated circuit of claim 5, further comprising an analyzer coupled to the memory via a bus for determining whether the at least the stored portion of the digitized baseband signal is within a predetermined limit.

7. The integrated circuit of claim 6, wherein the analyzer is a spectrum analyzer.

8. The integrated circuit of claim 6, wherein the analyzer is a processor capable of computing an error metric of the at least the stored portion of the digitized baseband signal.

9. A method of testing an integrated circuit comprising:

coupling a receiver portion of a radio frequency (RF) transceiver at a first receiver input to a transmitter portion of the transceiver at a transmitter output in a loopback configuration during a test mode;

providing a phase locked loop (PLL) output signal to the transmitter portion and to a second receiver input of the receiver portion, the PLL output signal during normal operation being used by the transmitter portion during a transmit mode and being used by the receiver portion during a receive mode;

generating the PLL output signal based on a transmitter modulation signal received at the PLL during the test mode;

receiving at the first receiver input a signal output from the transmitter portion;

receiving at the second receiver input the PLL output signal;

performing a mixing function, in the receiver portion, the function having inputs including a signal received at the first receiver input receiver input and a signal received at the second receiver input; and

determining a test result based on an output of the mixing function.

10. The method of claim 9, wherein the transmitter portion and the receiver portion are operated concurrently during the test mode.

11. The method of claim 9, wherein generating the PLL output signal provides a predetermined constant envelope modulation signal to the transmitter portion and to the second receiver input of the receiver portion.

12. The method of claim 11, wherein the predetermined constant envelope modulation is characterized as a tone modulation.

13. The method of claim 9, further comprising outputting an in-phase receiver signal at a first output of the receiver portion and a quadrature receiver signal at a second output of the receiver portion wherein each of the in-phase receiver signal and the quadrature receiver signal has a frequency that is twice the frequency of a corresponding signal output from the transmitter portion.

14. The method of claim 13, further comprising coupling a signal processor to the first output and to the second output of the receiver portion for generating a digital baseband signal representative of the RF signal received at the first receiver input.

15. The method of claim 14, further comprising storing in a memory at least a portion of the digitized baseband signal representative of the RF signal received at the first receiver input.

16. The method of claim 15, further comprising analyzing the at least a portion of the digitized baseband signal representative of the RF signal stored in the memory for distortions introduced in loopback configuration.

17. The method of claim 16, wherein the analyzing the at least a portion of the digitized baseband signal representative of the RF signal stored in the memory includes computing an error metric of the at least a portion of the digitized baseband signal representative of the RF signal stored in the memory.

18. The method of claim 9, further comprising testing a circuit module concurrently while testing the transceiver.

19. A method of testing a radio frequency (RF) transceiver comprising:

during a test mode;

providing a RF transceiver having a first receiver portion input coupled to a transmitter portion output in a loopback configuration;

performing a loopback test during which a phase locked loop (PLL) output is coupled to a second receiver portion input and to the transmitter portion, the PLL providing at the output a modulated PLL signal based on a transmitter modulation signal; and

mixing a signal received at the first receiver input portion with a signal received at the second receiver portion input;

during normal operation;

coupling the PLL output to the transmitter portion during a transmit mode; and

coupling the PLL output to the receiver portion during a receive mode.

20. The method of claim 19, wherein during a test mode further comprises:

receiving at the first receiver portion input a signal from the transmitter portion output; and

determining whether the received signal is within a predetermined limit.