Device including test circuit

• US 9,588,172 B2
• Filed: 02/04/2015
• Issued: 03/07/2017
• Est. Priority Date: 02/07/2014
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kurokawa, Yoshiyuki
• Primary Examiner(s): Laballe, Clayton E
• Assistant Examiner(s): Sanghera, Jas
• Application Number:
  US14/613,560
• Publication Number:
  US 20150226791A1
• Time in Patent Office: 762 Days
• US Class Current: 1/1
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/31813 Test pattern generators

Abstract

Provided is a device capable of generating test patterns even after the design stage. The area of a circuit which is included in the device and unnecessary during normal operation can be reduced. The device includes a first circuit and a second circuit. The second circuit includes a plurality of third circuits, a plurality of fourth circuits, and a fifth circuit and has a function of generating a signal for testing operation of the first circuit and a function of operating as part of the first circuit. The fourth circuit has a function of storing a first data and a function of storing a second data. The fifth circuit has a function of writing the first data to the plurality of fourth circuits, a function of writing the second data to the plurality of fourth circuits, and a function of reading the second data from the plurality of fourth circuits.

Claims

1. A device comprising:

a first circuit; and

a second circuit comprising;

a plurality of third circuits;

a plurality of fourth circuits; and

a fifth circuit,

wherein the second circuit is configured to generate a signal for testing operation of the first circuit and configured to operate as a memory of the first circuit,

wherein each of the plurality of fourth circuits comprises a first inverter and a second inverter, the second inverter comprising an input terminal electrically connected to an output terminal of the first inverter and an output terminal electrically connected to an input terminal of the first inverter,

wherein each of the plurality of fourth circuit is configured to store a first data and configured to store a second data,

wherein the fifth circuit is configured to write the first data to the plurality of fourth circuits,

wherein the fifth circuit is configured to write the second data to the plurality of fourth circuits and read the second data from the plurality of fourth circuits,

wherein the first data is to control conduction between the plurality of third circuits,

wherein each of the plurality of fourth circuits comprises a first transistor and a second transistor,

wherein one of a source and a drain of the first transistor and a gate of the second transistor are electrically connected to the input terminal of the first inverter, and

wherein the first transistor includes a first channel formation region in an oxide semiconductor layer.

2. The device according to claim 1,

wherein the second circuit is configured to operate as a cache memory of the first circuit.

3. The device according to claim 1,

wherein the first data is generated in accordance with serial data input to the fifth circuit.

4. The device according to claim 1,

wherein the second data is generated in accordance with parallel data input to the fifth circuit.

5. The device according to claim 1,

wherein the second transistor includes a second channel formation region comprising silicon.

6. The device according to claim 1,

wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

7. The device according to claim 6,

wherein the oxide semiconductor layer is a CAAC-OS film.

8. The device according to claim 1, wherein each of the plurality of third circuits is configured to store the first data to change a circuit configuration of the plurality of third circuits.

9. A device comprising:

a first circuit; and

a second circuit comprising;

a plurality of third circuits;

a plurality of fourth circuits; and

a fifth circuit,

wherein the second circuit is configured to generate a signal for testing operation of the first circuit in a first period and configured to operate as a memory of the first circuit in a second period,

wherein each of the plurality of fourth circuits comprises a first inverter and a second inverter, the second inverter comprising an input terminal electrically connected to an output terminal of the first inverter and an output terminal electrically connected to an input terminal of the first inverter,

wherein each of the plurality of fourth circuits is configured to store a first data and configured to store a second data,

wherein the fifth circuit is configured to write the first data to the plurality of fourth circuits in the first period,

wherein the fifth circuit is configured to write the second data to the plurality of fourth circuits and read the second data from the plurality of fourth circuits in the second period,

wherein the first data is to control conduction between the plurality of third circuits,

wherein the first period is a period of an operation test of the first circuit,

wherein each of the plurality of fourth circuits comprises a first transistor and a second transistor,

wherein one of a source and a drain of the first transistor and a gate of the second transistor are electrically connected to the input terminal of the first inverter, and

wherein the first transistor includes a first channel formation region in an oxide semiconductor layer.

10. The device according to claim 9,

wherein the second circuit is configured to operate as a cache memory of the first circuit in the second period.

11. The device according to claim 9,

wherein the first data is generated in accordance with serial data input to the fifth circuit.

12. The device according to claim 9,

wherein the second data is generated in accordance with parallel data input to the fifth circuit.

13. The device according to claim 9,

wherein the second transistor includes a second channel formation region comprising silicon.

14. The device according to claim 9,

wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

15. The device according to claim 14,

wherein the oxide semiconductor layer is a CAAC-OS film.

16. The device according to claim 9, wherein each of the plurality of third circuits is configured to store the first data to change a circuit configuration of the plurality of third circuits.