Link power savings with state retention

• US 9,588,575 B2
• Filed: 07/01/2014
• Issued: 03/07/2017
• Est. Priority Date: 06/30/2009
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Frodsham, Robin Tim, Cherukuri, Naveen, Wilcox, Jeffrey, Iyer, Venkatraman, Bilgin, Selim, Dunning, David S., Schoenborn, Theodore Z., Dabral, Sanjay
• Primary Examiner(s): Lee, Nhan
• Application Number:
  US14/321,402
• Publication Number:
  US 20150074440A1
• Time in Patent Office: 980 Days
• Field of Search: 455/41.2, 455/68, 455/69, 455/507, 455/522, 455/550.1, 455/552.1, 455/553.1, 455/572, 455/574, 370310-318, 370/338
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: H04W 52/0219 where the power saving management affects multiple terminals
• CPC Class Codes: H04W 52/0229 where the received signal is a wanted signal
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

Methods and apparatus relating to link power savings with state retention are described. In one embodiment, one or more components of two agents coupled via a serial link are turned off during idle periods while retaining link state in each agent. Other embodiments are also disclosed.

Claims

1. An apparatus comprising:

a first agent to be coupled to a second agent via a link, the first agent to;

assert a link entry signal to cause physical layer associated with the first agent to send an in-band reset signal to the second agent; and

enter the low power link state in response to an acknowledgement message to the link entry signal from the second agent;

wherein an electrical sub-block is to be turned off and power is to be maintained at a logical sub-block of the first agent in the low power link state to preserve configuration of the physical layer associated with the first agent.

2. The apparatus of claim 1, wherein the electrical sub-block comprises a phase locked loop (PLL) clock.

3. The apparatus of claim 1, wherein all lane transmitter and receivers and forwarded clocks of the link are to be disabled during the low power link state.

4. The apparatus of claim 1, wherein the low power link state comprises the lowest power state available to the link without removing its power supplies.

5. The apparatus of claim 1, wherein the acknowledgement comprises an in-band reset signal from the physical layer associated with the second agent.

6. The apparatus of claim 1, wherein the second agent is to exit the low power link state in response to a signal from the first agent.

7. The apparatus of claim 1, wherein the first agent is to exit the low power link state in response to a signal from the second agent.

8. The apparatus of claim 1, wherein the first agent is to detect terminations on the link during the low power link state.

9. The apparatus of claim 8, wherein a detect hold-off time is to be applied in the detection of the terminations.

10. The apparatus of claim 8, wherein the first agent is further to qualify detection of the terminations.

11. The apparatus of claim 1, wherein both directions of the link are to enter the low power link state.

12. The apparatus of claim 1, wherein the second agent is transmit the acknowledgement message in response to entry of a physical layer associated with the second agent into the low power link state.

13. An apparatus comprising:

a controller to interface between at least a first processor to recognize a first instruction set and second processor to recognize a second instruction set that is different from the first instruction set, the controller comprising interface logic to couple to a link comprising a plurality of lanes;

the interface logic to;

send a link entry signal to indicate that a physical layer is to enter a low power link state, wherein the low power link state comprises a lowest power state available to the link without removing power supplies to the link; and

enter the low power link state in response to an acknowledgement to the link entry signal, wherein an electrical sub-block of the physical layer is to be turned off and a logical sub-block of the physical layer is to be functionally shut down with power maintained at the logical sub-block in the low power link state to preserve configuration of the physical layer.

14. A method comprising:

asserting a link entry signal to cause a physical layer associated with a first agent to enter a low power link state and send an in-band reset signal to a second agent;

receiving an acknowledgment from the second agent, wherein the second agent is to transmit the acknowledgement message in response to a physical layer associated with second agent entering the low power link state; and

causing the first agent to enter the low power link state in response to the acknowledgement;

wherein an electrical sub-block is to be turned off and power is to be maintained at a logical sub-block of the first agent in the low power link state to preserve configuration of the physical layer associated with the first agent.

15. A system comprising:

a first agent; and

a second agent communicatively coupled to the first agent via a serial data link;

wherein the first agent is to send a signal to the second agent to indicate an attempt to enter a low power link state, the second agent is to enter the low power link state based on the signal and send an acknowledgment to the first agent, and the first agent is to enter the low power link state based on the acknowledgment, wherein clock circuitry of the first agent is to be turned-off and power is to be maintained at a logical sub-block of the first agent to maintain configuration of a physical layer of the first agent during the low power link state.

16. The system of claim 15, wherein the first and second agents are agents on a same computing chip package.

17. The system of claim 16, wherein the first and second agents are agents on a same die on the computing chip package.

18. The system of claim 16, wherein the first and second agents are agents on different die on the computing chip package.

19. The system of claim 15, wherein the first and second agents each comprise respective physical layer logic and respective link layer logic.

20. The system of claim 19, wherein entry and exit of the low power link state is to be initiated by the link layer logic.