Multi-stage programming at a storage device using multiple instructions from a host

• US 9,588,701 B2
• Filed: 09/09/2014
• Issued: 03/07/2017
• Est. Priority Date: 09/09/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Shaharabany, Amir, Oshinsky, Hadas
• Primary Examiner(s): Tran, Denise
• Application Number:
  US14/481,308
• Publication Number:
  US 20160070488A1
• Time in Patent Office: 910 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 2206/1014 One time programmable [OTP] memory, e.g. PROM, WORM
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0626 Reducing size or complexity of storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0665 at area level, e.g. provisioning of virtual or logical volumes
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits

Abstract

A method performed by a data storage device includes receiving, from a host device, a first instruction of a first set of instructions to write a first group of pages of data to a memory of the data storage device and receiving a second instruction of the first set of instructions to write the first group of pages of data. A first stage of a multi-stage programming operation is performed at a first physical address of the memory using a first copy of the first group of pages, and a second stage of the multi-stage programming operation is performed at the first physical address of the memory using a second copy of the first group of pages. The first copy and the second copy are received from the host device in association with the first instruction and the second instruction, respectively.

Claims

1. A method comprising:

in a data storage device, performing;

receiving, from a first command queue of a host device, a first instruction of a first set of instructions to write a first group of pages of data to a memory of the data storage device;

receiving, from a second command queue of the host device, a second instruction of the first set of instructions to write the first group of pages of data to the memory of the data storage device;

performing a first stage of a first multi-stage programming operation at storage elements corresponding to a first physical address of the memory using a first copy of the first group of pages, wherein the first copy is received from the host device in association with the first instruction; and

performing a second stage of the multi-stage programming operation at the storage elements corresponding to the first physical address of the memory using a second copy of the first group of pages, wherein the second copy is received from the host device in association with the second instruction.

2. The method of claim 1, wherein the memory comprises a three bits per cell flash memory, wherein the multi-stage programming operation is a three-stage programming operation, and wherein the first group includes three pages of data.

3. The method of claim 1, further comprising:

receiving a first instruction of a second set of instructions to write a second group of pages of data to the memory; and

performing a first stage of a second multi-stage programming operation at storage elements corresponding to a second physical address of the memory using a first copy of the second group of pages, wherein the first copy of the second group of pages is received from the host device in association with the first instruction of the second set of instructions, and wherein the first stage of the second multi-stage programming operation is performed after the first stage of the first multi-stage programming operation and before the second stage of the first multi-stage programming operation.

4. The method of claim 1, wherein the first command queue and the second command queue comprise universal flash storage (UFS) command queues.

5. The method of claim 1, wherein the first group of pages of data is stored in a host memory of the host device, wherein the first copy of the first group of pages is retrieved from the host memory responsive to a first request of the data storage device, and wherein the second copy of the first group of pages is retrieved from the host memory responsive to a second request of the data storage device.

6. The method of claim 1, further comprising:

receiving, from the host device, another instruction of the first set of instructions to write the first group of pages of data to the memory of the data storage device; and

in response to a verify operation indicating that the first group of pages is not reliably stored in a multi-level cell (MLC) portion of the memory, storing another copy of the first group of pages in a single-level cell (SLC) portion of the memory, wherein the another copy is received from the host device in association with the another instruction.

7. The method of claim 1, wherein the memory includes a three-dimensional (3D) memory that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate, and wherein the data storage device includes circuitry associated with operation of the memory cells.

8. A data storage device comprising:

a memory; and

a controller coupled to the memory, wherein the controller is configured to receive, from a first command queue of a host device, a first instruction of a first set of instructions to write a first group of pages of data to the memory and to receive, from a second command queue of the host device, a second instruction of the first set of instructions to write the first group of pages of data to the memory,

wherein the controller is further configured to perform a first stage of a first multi-stage programming operation at storage elements corresponding to a first physical address of the memory using a first copy of the first group of pages, wherein the first copy is accessible from the host device in association with the first instruction, and to perform a second stage of the multi-stage programming operation at the storage elements corresponding to the first physical address of the memory using a second copy of the first group of pages, wherein the second copy is accessible from the host device in association with the second instruction.

9. The data storage device of claim 8, wherein the memory comprises a three bits per cell flash memory, wherein the multi-stage programming operation is a three-stage programming operation, and wherein the first group includes three pages of data.

10. The data storage device of claim 8, wherein the controller is configured to receive a first instruction of a second set of instructions to write a second group of pages of data to the memory and to perform a first stage of a second multi-stage programming operation at storage elements corresponding to a second physical address of the memory using a first copy of the second group of pages, wherein the controller is configured to receive the first copy of the second group of pages from the host device in association with the first instruction of the second set of instructions, and wherein the controller is configured to perform the first stage of the second multi-stage programming operation after the first stage of the first multi-stage programming operation and before the second stage of the first multi-stage programming operation.

11. The data storage device of claim 8, wherein the first command queue and the second command queue comprise universal flash storage (UFS) command queues.

12. The data storage device of claim 8, wherein the controller is configured to receive, from the host device, another instruction of the first set of instructions to write the first group of pages of data to the memory of the data storage device and, in response to a verify operation indicating that the first group of pages is not reliably stored in a multi-level cell (MLC) portion of the memory, to store another copy of the first group of pages in a single-level cell (SLC) portion of the memory, wherein the another copy is received from the host device in association with the another instruction.

13. The data storage device of claim 8, wherein the memory includes a three-dimensional (3D) memory that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate, and wherein the data storage device includes circuitry associated with operation of the memory cells.

14. A data storage device comprising:

a memory; and

a controller coupled to the memory, wherein the controller is configured to receive, from a host device, a first instruction of a first set of instructions to write a first group of pages of data to the memory and to receive, from the host device, a second instruction of the first set of instructions to write the first group of pages of data to the memory,

wherein the controller is further configured to perform a first stage of a first multi-stage programming operation at storage elements corresponding to a first physical address of the memory using a first copy of the first group of pages, wherein the first copy is accessible from the host device in association with the first instruction, and to perform a second stage of the multi-stage programming operation at the storage elements corresponding to the first physical address of the memory using a second copy of the first group of pages, wherein the second copy is accessible from the host device in association with the second instruction, and

wherein the controller is configured to receive a first instruction of a second set of instructions to write a second group of pages of data to the memory and to perform a first stage of a second multi-stage programming operation at storage elements corresponding to a second physical address of the memory using a first copy of the second group of pages, wherein the controller is configured to receive the first copy of the second group of pages from the host device in association with the first instruction of the second set of instructions, and wherein the controller is configured to perform the first stage of the second multi-stage programming operation after the first stage of the first multi-stage programming operation and before the second stage of the first multi-stage programming operation.

15. The data storage device of claim 14, wherein the controller is configured to receive, from the host device, another instruction of the first set of instructions to write the first group of pages of data to the memory of the data storage device and, in response to a verify operation indicating that the first group of pages is not reliably stored in a multi-level cell (MLC) portion of the memory, to store another copy of the first group of pages in a single-level cell (SLC) portion of the memory, wherein the another copy is received from the host device in association with the another instruction.

16. The data storage device of claim 15, wherein the controller is configured to receive the first instruction of the first set of instructions from a first command queue of the host device and to receive the second instruction of the first set of instructions from a second command queue of the host device.

17. A data storage device comprising:

a memory; and

a controller coupled to the memory, wherein the controller is configured to receive, from a host device, a first instruction of a first set of instructions to write a first group of pages of data to the memory and to receive, from the host device, a second instruction of the first set of instructions to write the first group of pages of data to the memory,

wherein the controller is further configured to perform a first stage of a first multi-stage programming operation at storage elements corresponding to a physical address of the memory using a first copy of the first group of pages, wherein the first copy is accessible from the host device in association with the first instruction, and to perform a second stage of the multi-stage programming operation at the storage elements corresponding to the physical address of the memory using a second copy of the first group of pages, wherein the second copy is accessible from the host device in association with the second instruction, and

wherein the controller is configured to receive, from the host device, another instruction of the first set of instructions to write the first group of pages of data to the memory of the data storage device and, in response to a verify operation indicating that the first group of pages is not reliably stored in a multi-level cell (MLC) portion of the memory, to store another copy of the first group of pages in a single-level cell (SLC) portion of the memory, wherein the another copy is received from the host device in association with the another instruction.

18. A method comprising:

in a data storage device, performing;

receiving, from a host device, a first instruction of a first set of instructions to write a first group of pages of data to a memory of the data storage device;

receiving, from the host device, a second instruction of the first set of instructions to write the first group of pages of data to the memory of the data storage device;

performing a first stage of a first multi-stage programming operation at storage elements corresponding to a first physical address of the memory using a first copy of the first group of pages, wherein the first copy is received from the host device in association with the first instruction;

performing a second stage of the multi-stage programming operation at the storage elements corresponding to the first physical address of the memory using a second copy of the first group of pages, wherein the second copy is received from the host device in association with the second instruction;

receiving a first instruction of a second set of instructions to write a second group of pages of data to the memory; and

performing a first stage of a second multi-stage programming operation at storage elements corresponding to a second physical address of the memory using a first copy of the second group of pages, wherein the first copy of the second group of pages is received from the host device in association with the first instruction of the second set of instructions, and wherein the first stage of the second multi-stage programming operation is performed after the first stage of the first multi-stage programming operation and before the second stage of the first multi-stage programming operation.

19. The method of claim 18, further comprising:

receiving, from the host device, a third instruction of the first set of instructions to write the first group of pages of data to the memory of the data storage device; and

in response to a verify operation indicating that the first group of pages is not reliably stored in a multi-level cell (MLC) portion of the memory, storing a third copy of the first group of pages in a single-level cell (SLC) portion of the memory, wherein the third copy is received from the host device in association with the third instruction.

20. A method comprising:

in a data storage device, performing;

receiving, from a host device, a first instruction of a first set of instructions to write a first group of pages of data to a memory of the data storage device;

receiving, from the host device, a second instruction of the first set of instructions to write the first group of pages of data to the memory of the data storage device;

performing a first stage of a first multi-stage programming operation at storage elements corresponding to a physical address of the memory using a first copy of the first group of pages, wherein the first copy is received from the host device in association with the first instruction;

performing a second stage of the multi-stage programming operation at the storage elements corresponding to the physical address of the memory using a second copy of the first group of pages, wherein the second copy is received from the host device in association with the second instruction;

receiving, from the host device, a third instruction of the first set of instructions to write the first group of pages of data to the memory of the data storage device; and

in response to a verify operation indicating that the first group of pages is not reliably stored in a multi-level cell (MLC) portion of the memory, storing a third copy of the first group of pages in a single-level cell (SLC) portion of the memory, wherein the third copy is received from the host device in association with the third instruction.