Flash memory system

• US 9,588,883 B2
• Filed: 04/25/2012
• Issued: 03/07/2017
• Est. Priority Date: 09/23/2011
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: Conversant Intellectual Property Management Inc (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: Kim, Jin-Ki
• Primary Examiner(s): Thammavong, Prasith
• Application Number:
  US13/455,780
• Publication Number:
  US 20130080730A1
• Time in Patent Office: 1,777 Days
• Field of Search: 711/103
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A method and system for controlling an MBC configured flash memory device to store data in an SBC storage mode, or a partial MBC storage mode. In a full MBC storage mode, pages of data are programmed sequentially from a first page to an Nth page for each physical row of memory cells. Up to N virtual page addresses per row of memory cells accompany each page to be programmed for designating the virtual position of the page in the row. For SBC or partial MBC data storage, a flash memory controller issues program command(s) to the MBC memory device using less than the maximum N virtual page addresses for each row. The MBC memory device sequentially executes programming operations up to the last received virtual page address for the row.

Claims

1. A method for programming a multiple bit per cell (MBC) flash memory device configured to store up to N pages of data per physical row, N being an integer greater than one, the method comprising:

issuing a group of program commands for programming multiple pages of data to a subdivision having at least one physical row of the flash memory device,

the group of program commands being limited to addressing a subset of logical page addresses selected from all possible logical page addresses corresponding to each of the at least one physical row, where each program command comprises a row address having at least one bit representing a selected physical row and at least one bit representing a logical page address of the subset of logical page addresses corresponding to the selected physical row; and

programming less than N pages to each of the at least one physical row of the flash memory device in response to the subset of logical page addresses indicated in the row addresses in the program commands.

2. The method of claim 1, further comprising:

accessing a mapping table containing storage mode information for each subdivision of the flash memory device prior to issuing the group of program commands.

3. The method of claim 2, wherein the accessing the mapping table includes:

selecting the subdivision having a partial MBC storage mode where less than N pages of data are stored per physical row.

4. The method of claim 3, further comprising:

selecting the subset of logical page addresses corresponding to the partial MBC storage mode.

5. The method of claim 4, wherein all the possible logical page addresses corresponding to each of the at least one physical row includes sequential page addresses starting with a lower page address and ending with an upper page address.

6. The method of claim 5, wherein the subset of logical page addresses includes the lower page address up to an intermediate page address between the lower page address and the upper page address for each of the at least one physical row.

7. The method of claim 5, wherein the subset of logical page addresses include only lower page address for each of the at least one physical row.

8. The method of claim 5, wherein issuing includes iteratively providing program command packets each containing one page of the multiple pages of data and one of the subset of logical page addresses.

9. The method of claim 8, wherein the issuing includes:

providing M program command packets for programming M pages of the multiple pages of data to one physical row of the flash memory device, where M is an integer value less than N.

10. The method of claim 8, wherein the issuing includes:

iteratively providing one program command packet for programming one page of the multiple pages of data to one physical row of the flash memory device.

11. The method of claim 1, further comprising:

receiving a host request to program the multiple pages of data in a partial MBC storage mode prior to issuing the group of program commands.

12. The method of claim 1, further comprising:

receiving a host request to program the multiple pages of data in a full MBC storage mode prior to issuing the group of program commands.

13. The method of claim 12, including determining that a maximum number of MBC program/erase cycles for the subdivision has been reached.

14. The method of claim 13, further comprising:

selecting another subdivision configured for programming the multiple pages of data in the full MBC storage mode, and setting the subdivision to a partial MBC storage mode.

15. The method of claim 14, wherein the full MBC storage mode includes a two-bit per cell storage mode, and the partial MBC storage mode includes a one-bit per cell storage mode.

16. A system comprising:

a memory controller configured to issue program commands limited to addressing a subset of logical page addresses selected from all possible logical page addresses corresponding to each physical row of a memory device, where each program command comprises a row address having at least one bit representing a selected physical row and at least one bit representing a logical page address of the subset of logical page addresses corresponding to the selected physical row, the memory device comprising;

a multiple bit per cell (MBC) memory device configured to

store a maximum of N pages per physical row, N being an integer greater than one, and

program less than N pages per physical row in response to the subset of logical page addresses indicated in the row addresses in the program commands received from the memory controller.

17. The system of claim 16, wherein the memory controller includes:

a mapping table for storing meta-data corresponding to subdivisions of the memory device.

18. The system of claim 17, wherein the mapping table is configured to include storage mode information for each of the subdivisions.

19. The system of claim 18, wherein the mapping table is configured to include address binding information associated with the storage mode for each of the subdivisions.

20. The system of claim 19, wherein the memory controller includes:

control circuitry for accessing the mapping table and providing the program commands in response to the meta-data of the mapping table.

21. The system of claim 20, wherein each of the program commands includes:

a page of data, address information for selecting a subdivision of the memory device and a physical row within the subdivision, and

a logical page address for the page of data to be programmed in the physical row.

22. The system of claim 21, wherein:

the memory device is configured to store a maximum of N=2 pages per physical row, and each of the two pages per physical row are addressable by an upper page address and a lower page address.

23. The system of claim 22, wherein:

the upper page address has a first least significant bit, and

the lower page address has a second least significant bit different from the first least significant bit.

24. The system of claim 17, wherein the subdivisions of the memory device includes a memory block.

25. The system of claim 17, wherein the subdivisions of the memory device includes a sub-block of a memory block.

26. The system of claim 17, wherein the subdivisions of the memory device includes a physical row of a memory block.

27. A method for programming a multiple bit per cell (MBC) flash memory device configured for storing up to N bits per cell, where N is an integer greater than one, the method comprising:

receiving a host request to program data pages;

determining the data pages are to be programmed in a partial MBC storage mode where less than N virtually addressable data pages are stored in each physical row of the flash memory device;

accessing a mapping table containing meta-data for the flash memory device to select a subdivision of the MBC flash memory device configured in the partial MBC storage mode; and

issuing at least one program command for programming the data pages to the subdivision using virtual page addresses limited to a subset of less than N possible virtual page addresses for programming pages to each physical row, where each program command comprises a row address having at least one bit representing a selected physical row and at least one bit representing a virtual page address of the subset of less than N possible virtual page addresses corresponding to the selected physical row.

28. The method of claim 27, wherein:

N=2 and possible virtual page addresses include a lower page address and an upper page address, and

issuing includes iteratively issuing program commands, each including a data page and a lower page address.

29. The method of claim 27, wherein:

N>

2 and possible virtual page addresses include a lower page address, an upper page address, and at least one intermediate page address between the lower page address and the upper page address, and

issuing includes iteratively issuing program commands each including a data page and one of the lower page address and the at least one intermediate page address.