Host apparatus to independently schedule maintenance operations for respective virtual block devices in the flash memory dependent on information received from a memory controller

• US 9,588,904 B1
• Filed: 02/25/2016
• Issued: 03/07/2017
• Est. Priority Date: 09/09/2014
• Status: Active Grant

• Current Assignee: Radian Memory Systems, LLC
• Original Assignee: Radian Memory Systems, Inc.
• Inventors: Lercari, Robert, Chen, Alan, Jadon, Mike, Robertson, Craig, Kuzmin, Andrey V.
• Primary Examiner(s): Rigol, Yaima
• Assistant Examiner(s): Gossage, Glenn
• Application Number:
  US15/053,372
• Time in Patent Office: 376 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/109 for multiple virtual address spaces, e.g. segmentation G06F12/1036 takes precedence
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0662 Virtualisation aspects
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

Hierarchical address virtualization within a memory controller and configurable block device allocation are disclosed. Respective virtual block devices (VBDs) are defined in flash memory managed by a common memory controller, with data access managed using address virtualization techniques. The common memory controller then tracks the need for maintenance operations independently for each VBD. Information may be received from the common memory controller regarding the need for maintenance operations in respective virtual block devices (VBDs), and commands are then selectively issued to the common memory controller in a manner so as to independently schedule these operations for the respective VBDs; performance of maintenance operations by the memory controller in a first VBD is unconstrained by performance characteristics associated with a second VBD.

Claims

1. An apparatus to transmit data access requests to a memory controller for flash memory, the apparatus comprising:

circuitry to assign non-overlapping logical address ranges to respective virtual block devices defined with respect to the flash memory, wherein each one of the respective virtual block devices is characterized by associated performance characteristics comprising a minimum time required to program a page of memory cells in the flash memory, a minimum time required to erase a block of memory cells in the flash memory, and a minimum time required to read a page of memory cells in the flash memory;

circuitry to receive from the memory controller, on an independent basis for each one of the respective virtual block devices, information identifying the need for a maintenance operation, the maintenance operation for each one of the respective virtual block devices comprising at least one of erase of an erase unit in the flash memory corresponding to the one of the respective virtual block devices or a data relocation operation for data stored in the flash memory corresponding to the one of the respective virtual block devices; and

circuitry to schedule issuance of commands to the memory controller, the commands to control the performance of maintenance operations in respective virtual block devices, in a manner such that the scheduling of commands to perform a maintenance operation in a first one of the respective virtual block devices is unconstrained by the performance characteristics associated with a second one of the respective virtual block devices.

2. The apparatus of claim 1, wherein the flash memory includes, for each of the virtual block devices, a set of access-enabled structural elements and a set of access-reserved structural elements, each access-enabled structural element and each access-reserved structural element having an associated physical address, and wherein the apparatus is to, independently, for each of the respective virtual block devices:

identify a size associated with a corresponding set of access-enabled structural elements;

assign the non-overlapping logical address range for the respective virtual block device in dependence on the size, such that the non-overlapping address range for the respective virtual block device represents a subset of physical flash memory space associated with the respective virtual block device; and

programmably-configure the memory controller to map the non-overlapping address range for the respective virtual block device to the corresponding set of access-enabled structural elements.

3. The apparatus of claim 2, wherein the flash memory includes flash memory dies, and wherein:

the apparatus is to, for each of the respective virtual block devices, programmably-configure the memory controller to map the non-overlapping address ranges to a configurable number of the flash memory dies, the configurable number being one or more; and

the configurable number is free to be different for a first one of the respective virtual block devices than for a second one of the respective virtual block devices.

4. The apparatus of claim 3, wherein the apparatus is further operable to, for at least one of the respective virtual block devices, programmably-configure the memory controller such that the access-enabled set of structural elements for the at least one of the virtual block devices comprises one or more discrete flash memory dies, and such that the reserved set of structural elements for the at least one comprises one or more discrete flash memory dies.

5. The apparatus of claim 1, wherein the flash memory is coupled to the memory controller by multiple independent communication channels, and wherein:

the apparatus is to

identify a number of channels to be associated with each respective virtual block device, the number being one or more, and

programmably-configure the memory controller to map the logical address ranges for each respective virtual block device to the number of channels identified for the respective virtual block device; and

the numbers for the respective virtual block devices can be different from one another.

6. The apparatus of claim 1, wherein the flash memory comprises first structural elements and second structural elements, and wherein the apparatus further comprises circuitry to program the memory controller to operate at least one of the respective virtual block devices in a selective one of a first mode and a second mode, wherein in the first mode, successive writes are to be directed by the memory controller to successive ones of the first structural elements, and wherein in the second mode, successive writes are to be directed by the memory controller to successive ones of the second structural elements within a single one of the second structural elements.

7. The apparatus of claim 6, wherein the first structural elements comprise erase units of flash memory and the second structural elements comprise pages of flash memory.

8. The apparatus of claim 6, wherein the information identifying the need for a maintenance operation comprises at least one logical address associated with one of the respective virtual block devices, and wherein:

the circuitry to schedule issuance of commands, responsive to receipt of said information, is to schedule (a) movement of data corresponding to the at least one logical address to a different physical memory location associated with the one of the respective virtual block devices, and (b) erase of a physical memory location which previously stored the data; and

the circuitry to schedule issuance of commands is further to sequentially issue commands to perform the scheduled movement of the data and the erase of the physical memory location in dependence on the performance characteristics associated with the one of the respective virtual block devices.

9. The apparatus of claim 8, wherein the one of the respective virtual block devices is a first virtual block device, and wherein the circuitry to schedule issuance of commands is operable to issue one of a data read or data write command to the memory controller for performance in a second virtual block device different than the first virtual block device, the data read or write command to be performed concurrently with performance of at least one of the sequentially-issued commands and irrespective of the performance characteristics of the first virtual block device.

10. An apparatus comprising instructions stored on non-transitory machine-readable media, said apparatus to cause an electronic system to transmit data access requests to a memory controller for flash memory, said instructions when executed to cause at least one integrated circuit processor of the electronic system:

assign non-overlapping logical address ranges to respective virtual block devices defined with respect to the flash memory, wherein each one of the respective virtual block devices is characterized by associated performance characteristics comprising a minimum time required to program a page of memory cells in the flash memory, a minimum time required to erase a block of memory cells in the flash memory, and a minimum time required to read a page of memory cells in the flash memory;

receive from the memory controller, on an independent basis for each one of the respective virtual block devices, information identifying the need for a maintenance operation, the maintenance operation for each one of the respective virtual block devices comprising at least one of erase of an erase unit in the flash memory corresponding to the one of the respective virtual block devices or a data relocation operation for data stored in the flash memory corresponding to the one of the respective virtual block devices; and

schedule issuance of commands to the memory controller to perform maintenance operations in respective virtual block devices, in a manner such that the scheduling of commands to perform a maintenance operation in a first one of the respective virtual block devices is unconstrained by the performance characteristics associated with a second one of the respective virtual block devices.

11. The apparatus of claim 10, wherein the flash memory includes, for each of the virtual block devices, a set of access-enabled structural elements and a set of access-reserved structural elements, each access-enabled structural element and each access-reserved structural element having an associated physical address, and wherein the apparatus further comprises instructions that, when executed, are to cause the at least one integrated circuit processor to, independently, for each of the respective virtual block devices:

identify a size associated with a corresponding set of access-enabled structural elements;

assign the non-overlapping logical address range for the respective virtual block device in dependence on the size, such that the non-overlapping address range for the respective virtual block device represents a subset of physical flash memory space associated with the respective virtual block device; and

programmably-configure the memory controller to map the non-overlapping address range for the respective virtual block device to the corresponding set of access-enabled structural elements.

12. The apparatus of claim 11, wherein the flash memory includes flash memory dies, and wherein:

the apparatus further comprises instructions that, when executed, are to cause the at least one integrated circuit processor to, independently, for each of the respective virtual block devices, programmably-configure the memory controller to map the non-overlapping address ranges to a configurable number of the flash memory dies, the configurable number being one or more; and

the configurable number is free to be different for a first one of the respective virtual block devices than for a second one of the respective virtual block devices.

13. The apparatus of claim 12, wherein the apparatus further comprises instructions that, when executed, are to cause the at least one integrated circuit processor to, for at least one of the respective virtual block devices, programmably-configure the memory controller such that the access-enabled set of structural elements for the at least one of the virtual block devices comprises one or more discrete flash memory dies, and such that the reserved set of structural elements for the at least one comprises one or more discrete flash memory dies.

14. The apparatus of claim 10, wherein the flash memory is coupled to the memory controller by multiple independent communication channels, and wherein:

the apparatus further comprises instructions that, when executed, are to cause the at least one integrated circuit processor to

identify a number of channels to be associated with each respective virtual block device, the number being one or more, and

programmably-configure the memory controller to map the logical address ranges for each respective virtual block device to the number of channels identified for the respective virtual block device; and

the numbers for the respective virtual block devices can be different from one another.

15. The apparatus of claim 10, wherein the flash memory comprises first structural elements and second structural elements, and wherein the apparatus further comprises instructions that, when executed, are to cause the at least one integrated circuit processor to program the memory controller to operate at least one of the respective virtual block devices in a selective one of a first mode and a second mode, wherein in the first mode, successive writes are to be directed by the memory controller to successive ones of the first structural elements, and wherein in the second mode, successive writes are to be directed by the memory controller to successive ones of the second structural elements within a single one of the second structural elements.

16. The apparatus of claim 15, wherein the first structural elements comprise erase units of flash memory and the second structural elements comprise pages of flash memory.

17. The apparatus of claim 15, wherein the information identifying the need for a maintenance operation comprises at least one logical address associated with one of the respective virtual block devices, and wherein the apparatus further comprises instructions that, when executed, are to cause the at least one integrated circuit processor to:

schedule issuance of commands responsive to receipt of said information to perform (a) movement of data corresponding to the at least one logical address to a different physical memory location associated with the one of the respective virtual block devices, and (b) erase of a physical memory location which previously stored the data; and

sequentially issue the commands to perform the scheduled movement of the data and the erase of the physical memory location in dependence on the performance characteristics associated with the one of the respective virtual block devices.

18. The apparatus of claim 17, wherein the one of the respective virtual block devices is a first virtual block device, and wherein the apparatus further comprises instructions that, when executed, are to cause the at least one integrated circuit processor to issue one of a data read or data write command to the memory controller for performance in a second virtual block device different than the first virtual block device, the data read or write command to be performed concurrently with performance of at least one of the sequentially-issued commands and irrespective of the performance characteristics of the first virtual block device.

19. An apparatus to transmit data access requests to a memory controller for flash memory, the flash memory comprising flash memory dies controlled in common by the memory controller, the apparatus comprising:

circuitry to assign non-overlapping logical address ranges to respective virtual block devices defined with respect to the flash memory, wherein each one of the respective virtual block devices is associated with a respective subset of one or more of the flash memory dies on a mutually-exclusive basis relative to each other and wherein each one of the respective virtual block devices is characterized by associated performance characteristics comprising a minimum time required to program a page of memory cells in the flash memory, a minimum time required to erase a block of memory cells in the flash memory, and a minimum time required to read a page of memory cells in the flash memory;

circuitry to receive from the memory controller, on an independent basis for each one of the respective virtual block devices, information identifying the need for a maintenance operation in a particular die of the respective subset of the flash memory dies, the maintenance operation for each one of the respective virtual block devices comprising at least one of erase of an erase unit in the particular die or a data relocation operation for data stored in the particular die; and

circuitry to schedule issuance of commands to the memory controller, the commands to control performance of maintenance operations, in a manner such that the scheduling of commands to perform a maintenance operation in a first one of the respective virtual block devices is unconstrained by the performance characteristics associated with a second one of the respective virtual block devices.