Interrupt latency reduction

• US 9,588,916 B1
• Filed: 06/30/2014
• Issued: 03/07/2017
• Est. Priority Date: 03/12/2007
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Wright, David G.
• Primary Examiner(s): Zaman, Faisal M
• Application Number:
  US14/319,041
• Time in Patent Office: 981 Days
• Field of Search: 710260-269, 713300-600
• US Class Current: 1/1
• CPC Class Codes: G05F 1/10 Regulating voltage or current G05F1/02 takes precedence; for electric railways B60M3/02
• CPC Class Codes: G05F 1/46 wherein the variable actually regulated by the final control device is dc G05F1/625 takes precedence
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H03L 5/02 of power
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method in accordance with one embodiment of the invention can include detecting an interrupt request during execution of an instruction by a processor of an integrated circuit. Additionally, a clock signal frequency can be changed that is received by the processor. An interrupt service routine can be executed that corresponds to the interrupt request.

Claims

1. A method, comprising:

providing a first clock signal having a first frequency to a processor;

executing an instruction stream on the processor at the first frequency;

in response to detecting an interrupt request, changing the first frequency of the first clock signal to a second frequency;

storing processor status information associated with the instruction stream at the second frequency greater than the first frequency prior to executing an interrupt service routine;

executing the interrupt service routine on the processor at the second frequency;

restoring the processor status information at the second frequency;

changing the second frequency of the first clock signal to the first frequency; and

resuming execution of the instruction stream on the processor at the first frequency.

2. The method of claim 1, wherein providing the clock signal comprises generating an oscillator signal using a crystal-less programmable oscillator.

3. The method of claim 1, wherein providing the clock signal comprises multiplying an oscillator signal.

4. The method of claim 3, wherein providing the clock signal comprises dividing a signal generated by multiplying the oscillator signal.

5. The method of claim 1, wherein providing the clock signal comprises dividing an oscillator signal.

6. The method of claim 1, further comprising providing a second clock signal having a third frequency to a digital system while the processor is executing the instruction stream at the first frequency, wherein the digital system is separate from the processor.

7. The method of claim 6, further comprising providing the second clock having the third frequency to the digital system while processor is executing the interrupt service routine at the second frequency.

8. The method of claim 6, wherein the third frequency is equal to the first frequency.

9. The method of claim 6, wherein the third frequency is equal to the second clock frequency.

10. A method, comprising:

providing a first clock signal having a first frequency to a processor;

executing an instruction stream on the processor at the first frequency;

in response to detecting an interrupt request during execution of an instruction of the instruction stream, completing the execution of the instruction of the instruction stream at the first frequency;

changing the first frequency of the first clock signal to a second frequency;

storing processor status information associated with the instruction stream at the second frequency greater than the first frequency prior to executing an interrupt service routing;

executing an interrupt service routine on the processor at the second frequency;

restoring the processor status information;

changing the second frequency of the first clock signal to the first frequency; and

resuming execution of the instruction stream on the processor at the first frequency.

11. The method of claim 10, wherein providing the clock signal comprises generating an oscillator signal using a crystal-less programmable oscillator.

12. The method of claim 10, wherein providing the clock signal comprises multiplying an oscillator signal.

13. The method of claim 12, wherein providing the clock signal comprises dividing a signal generated by multiplying the oscillator signal.

14. The method of claim 10, wherein providing the clock signal comprises dividing an oscillator signal.

15. The method of claim 10, further comprising providing a second clock signal having a third frequency to a digital system while the processor is executing the instruction stream at the first frequency, wherein the digital system is separate from the processor.

16. The method of claim 15, further comprising providing the second clock having the third frequency to the digital system while processor is executing the interrupt service routine at the second frequency.

17. The method of claim 15, wherein the third frequency is equal to the first frequency.

18. The method of claim 15, wherein the third frequency is equal to the second frequency.