Integrated circuit using topology configurations

• US 9,589,601 B2
• Filed: 03/16/2015
• Issued: 03/07/2017
• Est. Priority Date: 03/16/2015
• Status: Active Grant

• Current Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.), Board of Regents of the University of Michigan (University of Michigan)
• Original Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.), Board of Regents of the University of Michigan (University of Michigan)
• Inventors: Khayatzadeh, Mahmood, Alioto, Massimo Bruno, Blaauw, David, Sylvester, Dennis Michael Chen, Bohra, Fakhruddin Ali
• Primary Examiner(s): Byrne, Harry W
• Application Number:
  US14/659,270
• Publication Number:
  US 20160276000A1
• Time in Patent Office: 722 Days
• Field of Search: 365/189.02
• US Class Current: 1/1
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 2207/002 Isolation gates, i.e. gates coupling bit lines to the sense amplifier
• CPC Class Codes: G11C 2207/005 Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
• CPC Class Codes: G11C 29/026 in sense amplifiers
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

Various implementations described herein may refer to and may be directed to circuitry for an integrated circuit using topology configurations. For instance, in one implementation, such circuitry may include a memory array having a plurality of memory cells. Such circuitry may also include one or more reconfigurable sense amplifier devices coupled to the memory array and configured to amplify differential voltage levels received from the memory array. The reconfigurable sense amplifier devices may include a plurality of sense amplifier circuits configured to be arranged in one of a plurality of topology configurations, where the topology configurations include a parallel configuration and a cross parallel configuration. The reconfigurable sense amplifier devices may also include one or more switches configured to set the plurality of sense amplifier circuits into the plurality of topological configurations based on one or more control bits.

Claims

1. An integrated circuit, comprising:

a memory array, comprising a plurality of memory cells; and

one or more reconfigurable sense amplifier devices coupled to the memory array and configured to amplify differential voltage levels received from the memory array, the one or more reconfigurable sense amplifier devices comprising;

a plurality of sense amplifier circuits configured to be arranged in one of a plurality of topology configurations, wherein the topology configurations comprise a parallel configuration and a cross parallel configuration; and

one or more switches configured to set the plurality of sense amplifier circuits into the plurality of topological configurations based on one or more control bits.

2. The integrated circuit of claim 1, wherein the switches comprise one or more pass-gate switches driven by the one or more control bits.

3. The integrated circuit of claim 2, wherein the one or more pass-gate switches are driven by the one or more control bits in conjunction with one or more combinational logic circuits.

4. The integrated circuit of claim 1, wherein the control bits are configured to arrange the plurality of sense amplifier circuits into a topology configuration having a least amount of offset voltage.

5. The integrated circuit of claim 1, wherein the one or more control bits are stored in one or more of the memory cells.

6. The integrated circuit of claim 1, wherein a total offset voltage of the one or more reconfigurable sense amplifier devices in a particular topology configuration comprises an average of individual offset voltages of the plurality of sense amplifier circuits used in the particular topology configuration.

7. The integrated circuit of claim 1, wherein the plurality of sense amplifier circuits comprise a first sense amplifier circuit and a second sense amplifier circuit, and wherein the one or more switches are configured to set the first sense amplifier circuit and the second sense amplifier circuit into one of four topology configurations.

8. The integrated circuit of claim 7, wherein the four topology configurations comprise:

a first configuration using the first sense amplifier circuit;

a second configuration using the second sense amplifier circuit;

a third configuration using the first sense amplifier circuit and the second sense amplifier circuit, wherein the first sense amplifier circuit and the second sense amplifier circuit are directly connected and in parallel; and

a fourth configuration using the first sense amplifier circuit and the second sense amplifier circuit, wherein the first sense amplifier circuit and the second sense amplifier are cross connected and in cross parallel.

9. The integrated circuit of claim 1, further comprising:

a first bit-line pair coupled to a respective memory cell of the memory array and to a respective reconfigurable sense amplifier device; and

a second bit-line pair coupled to the respective memory cell and to the respective reconfigurable sense amplifier device, wherein, during a read operation of the respective memory cell, the first bit-line pair or the second bit-line pair is selected to transmit data stored within the respective memory cell based on a readability of the first bit-line pair and the second bit-line pair.

10. The integrated circuit of claim 9, further comprising:

a first set of bit-line switches configured to couple the first bit-line pair to the respective reconfigurable sense amplifier device; and

a second set of bit-line switches configured to couple the second bit-line pair to the respective reconfigurable sense amplifier device, wherein the first bit-line pair or the second bit-line pair is selected using the first set of bit-line switches and the second set of bit-line switches.