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Integrated circuit using topology configurations

  • US 9,589,601 B2
  • Filed: 03/16/2015
  • Issued: 03/07/2017
  • Est. Priority Date: 03/16/2015
  • Status: Active Grant
First Claim
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1. An integrated circuit, comprising:

  • a memory array, comprising a plurality of memory cells; and

    one or more reconfigurable sense amplifier devices coupled to the memory array and configured to amplify differential voltage levels received from the memory array, the one or more reconfigurable sense amplifier devices comprising;

    a plurality of sense amplifier circuits configured to be arranged in one of a plurality of topology configurations, wherein the topology configurations comprise a parallel configuration and a cross parallel configuration; and

    one or more switches configured to set the plurality of sense amplifier circuits into the plurality of topological configurations based on one or more control bits.

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