Block refresh to adapt to new die trim settings
First Claim
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1. A system for adapting to trim set advancement, wherein trim set advancement is a change in trim sets over time, the system comprising:
- a semiconductor memory comprising a cell having a first charge level, the cell raised to the first charge level representing a value when the cell was programmed to the value with a first trim set;
a charge circuit configured to add a charge to the cell; and
a controller configured to direct the charge circuit to raise the first charge level of the cell to a second charge level that corresponds to the cell programmed to the value with a second trim set, the second trim set different than the first trim set.
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Abstract
Systems, apparatuses, and methods may be provided that adapt to trim set advancement. Trim set advancement may be a change in trim sets over time. A cell of a semiconductor memory may have a first charge level and be programmed with a first trim set. The cell may be reprogrammed by raising the first charge level to a second charge level that corresponds to the cell programmed with a second trim set.
16 Citations
21 Claims
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1. A system for adapting to trim set advancement, wherein trim set advancement is a change in trim sets over time, the system comprising:
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a semiconductor memory comprising a cell having a first charge level, the cell raised to the first charge level representing a value when the cell was programmed to the value with a first trim set; a charge circuit configured to add a charge to the cell; and a controller configured to direct the charge circuit to raise the first charge level of the cell to a second charge level that corresponds to the cell programmed to the value with a second trim set, the second trim set different than the first trim set. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method to adapt to a change in trim sets over time, the method comprising:
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programming a cell of a semiconductor memory with a first trim set, the cell having a charge level raised to a first charge level by the programming; and reprogramming the cell by raising the first charge level to a second charge level, the second charge level corresponding to the cell programmed with a second trim set that is different than the first trim set. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A memory device comprising:
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a semiconductor memory comprising a plurality of word lines, the word lines including a word line programmed with a first program setting, the programmed word line charged to a first charge level representative of a stored value at the first program setting; a controller configured to read the stored value from the programmed word line; and a charge circuit configured to add a charge to any of the word lines selected for programming, wherein the controller is further configured to direct the charge circuit to change the first charge level of the programmed word line to a second charge level, the second charge level representative of the stored value programmed with a second program setting, the second program setting different than the first program setting. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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21. A memory device comprising:
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a semiconductor memory comprising a plurality of word lines, the word lines including a word line programmed with a first program setting, the programmed word line charged to a first charge level representative of a stored value at the first program setting; a means for reading the stored value from the programmed word line; and a means for raising the first charge level of the programmed word line to a second charge level, the second charge level representative of the stored value programmed with a second program setting, the second program setting different than the first program setting.
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Specification