Fin cut enabling single diffusion breaks

• US 9,589,845 B1
• Filed: 05/23/2016
• Issued: 03/07/2017
• Est. Priority Date: 05/23/2016
• Status: Expired due to Fees

• Current Assignee: Elpis Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Jagannathan, Hemanth, Kanakasabapathy, Sivananda K., Paruchuri, Vamsi K., Reznicek, Alexander
• Primary Examiner(s): Valentine, Jami M
• Application Number:
  US15/161,868
• Time in Patent Office: 288 Days
• Field of Search: 438/433
• US Class Current: 1/1
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66803 with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A method is provided for forming a fin cut that enables a single diffusion break in very dense CMOS structures formed using bulk semiconductor substrates. A dummy gate is removed from a finned structure to expose the top regions of the fins, the bottom fin regions being within a shallow trench isolation region. Selective vapor phase etching follows sequential ion implantation of the top and bottom fin regions to form a diffusion break cut region. The non-implanted regions of the substrate and the shallow trench isolation region remain substantially intact during each etching procedure. Double diffusion break cut regions are also enabled by the method.

Claims

1. A method for forming a diffusion break in a finned semiconductor structure, comprising:

obtaining a finned semiconductor structure including a bulk semiconductor substrate including a substrate portion, a plurality of parallel fins extending from the substrate portion, a shallow trench isolation region, each of the fins including a top region extending above the shallow trench isolation region and a bottom region within the shallow trench isolation region, a plurality of parallel dummy gates extending over the fins and perpendicularly with respect to the fins, and spacers lining the dummy gates;

removing at least one of the dummy gates to form a space between a pair of the spacers and above at least a first of the parallel fins;

ion implanting the top region of the first fin to cause the formation of a top amorphous alloy fin region;

removing the top amorphous alloy fin region of the first fin using a chemical etch selective to the spacers, the shallow trench isolation region, and the substrate;

ion implanting a portion of the bottom region of the first fin following removing the top amorphous alloy fin region to cause the formation of a bottom amorphous alloy fin region, and

removing the bottom amorphous alloy fin region of the first fin using a chemical etch selective to the spacers, the shallow trench isolation region, and the substrate to form a recess within the shallow trench isolation region, the space and the recess forming a diffusion break cut region.

2. The method of claim 1, wherein the bulk semiconductor substrate comprises silicon, ion implanting the top and bottom regions of the first fin further includes implanting germanium in the top and bottom regions of the first fin, the top amorphous alloy fin region comprising silicon germanium, and the bottom amorphous alloy fin region comprising silicon germanium.

3. The method of claim 2, wherein the top and bottom amorphous alloy fin regions consist essentially of Si_1-xGe_x where x is at least 0.20.

4. The method of claim 3, wherein removing the top amorphous alloy fin region and the bottom amorphous alloy fin region comprises vapor phase etching.

5. The method of claim 4, wherein the vapor phase etching utilizes hydrogen chloride.

6. The method of claim 5, further including replacing one or more of the dummy gates with metal gates.

7. The method of claim 6, wherein the bulk semiconductor substrate consists essentially of monocrystalline silicon.

8. The method of claim 7, wherein the fins consist essentially of silicon or silicon germanium.

9. The method of claim 8, wherein the dummy gates comprise polysilicon.

10. The method of claim 8, further including forming first and second FinFETs electrically isolated by the diffusion break cut region.

11. The method of claim 2, wherein:

removing the at least one of the dummy gates forms the space above a plurality of the parallel fins,

ion implanting the top region of the first fin further includes implanting top regions of the plurality of the parallel fins to form top amorphous alloy fin regions within the plurality of the parallel fins;

removing the top amorphous alloy fin region of the first fin further includes removing the top amorphous alloy fin regions within the plurality of the parallel fins;

ion implanting the portion of the bottom region of the first fin further includes ion implanting portions of the bottom regions of the plurality of the parallel fins, thereby forming bottom amorphous alloy fin regions within the plurality of the parallel fins, and

removing the bottom amorphous alloy fin region of the first fin further includes removing the bottom amorphous alloy fin regions within the plurality of the parallel fins.

12. The method of claim 11, wherein ion implanting the top and bottom regions of the first fin and ion implanting portions of the bottom regions of the plurality of fins further includes implanting germanium such that the top and bottom amorphous alloy fin regions consist essentially of Si_1-xGe_x where x is at least 0.20.

13. The method of claim 12, wherein removing the top and bottom amorphous alloy fin regions comprises vapor phase etching.

14. The method of claim 13, wherein the vapor phase etching utilizes hydrogen chloride.

15. The method of claim of claim 14, further including depositing an oxide material within the space and recess.

16. The method of claim 14, wherein removing the bottom amorphous alloy fin regions within the plurality of parallel fins further includes leaving a portion of each fin extending above the substrate portion and within the shallow trench isolation region.

17. The method of claim 16, further including depositing dielectric material within the diffusion break cut region.

18. The method of claim 1, further including depositing dielectric material within the diffusion break cut region.

19. The method of claim 18, wherein the bulk semiconductor substrate comprises silicon, and ion implanting the top and bottom regions of the first fin further includes implanting germanium in the top and bottom regions of the first fin such that the top and bottom amorphous alloy fin regions consist essentially of Si_1-xGe_x where x is at least 0.20.

20. The method of claim 19, wherein removing the top and bottom amorphous alloy fin regions comprises vapor phase etching utilizing hydrogen chloride.