Structure and method of operation for improved gate capacity for 3D NOR flash memory

• US 9,589,982 B1
• Filed: 09/15/2015
• Issued: 03/07/2017
• Est. Priority Date: 09/15/2015
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Cheng, Cheng-Hsien, Lee, Chih-Wei, Ku, Shaw-Hung, Lu, Wen-Pin
• Primary Examiner(s): Payen, Marvin
• Assistant Examiner(s): Joy, Jeremy
• Application Number:
  US14/854,383
• Publication Number:
  US 20170077118A1
• Time in Patent Office: 539 Days
• US Class Current: 1/1
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

Embodiments of the present invention provide improved three-dimensional memory cells, arrays, devices, and/or the like and associated methods. In one embodiment, a three-dimensional memory cell is provided. The three-dimensional memory cell comprises a first conductive layer; a third conductive layer spaced apart from the first conductive layer; a channel conductive layer connecting the first conductive layer and the third conductive layer to form an opening having internal surfaces; a dielectric layer disposed along the internal surfaces of the opening surrounded by the first conductive layer, the channel conductive layer and the third conductive layer; and a second conductive layer interposed and substantially filling a remaining open portion formed by the dielectric layer. The first conductive layer, the dielectric layer, and the second conductive layer are configured to form a staircase structure.

Claims

1. A three-dimensional memory cell comprising:

a first conductive layer;

a third conductive layer spaced apart from the first conductive layer;

a channel conductive layer connecting the first conductive layer and the third conductive layer to form an opening having internal surfaces;

a dielectric layer disposed along the internal surfaces of the opening surrounded by the first conductive layer, the channel conductive layer and the third conductive layer; and

a second conductive layer interposed and substantially filling a remaining open portion formed by the dielectric layer,

wherein the first conductive layer, the dielectric layer, and the second conductive layer are configured to form a staircase structure.

2. The three-dimensional memory cell of claim 1, wherein the first conductive layer corresponds to at least one common source line.

3. The three-dimensional memory cell of claim 1, wherein the third conductive layer corresponds to at least one bit line.

4. The three-dimensional memory cell of claim 1, wherein the second conductive layer corresponds to at least one word line.

5. The three-dimensional memory cell of claim 1, wherein the dielectric layer comprises at least one of a block layer, a storage layer, or a tunnel layer.

6. The three-dimensional memory cell of claim 1, wherein the three-dimensional memory cell is one cell of a plurality of cells along a string of memory cells.

7. The three-dimensional memory cell of claim 1, wherein the dielectric layer comprises a lower oxide film, a nitride film, and an upper oxide film.

8. The three-dimensional memory cell of claim 1, wherein the insulating layer, the first conductive layer, the dielectric layer, and the second conductive layer are structured to connect the bit line in a staircase formation.

9. The three-dimensional memory cell of claim 8, wherein the staircase formation comprises a third conductive layer.