Interdigitated capacitor to integrate with flash memory
First Claim
1. An integrated circuit (IC), comprising:
- a semiconductor substrate including a flash memory region and a capacitor region;
a flash memory cell arranged over the flash memory region and including;
a polysilicon select gate arranged between first and second source/drain regions of the flash memory cell, and a control gate arranged alongside the select gate and separated from the select gate by a control gate dielectric layer; and
a capacitor arranged over the capacitor region and including;
a polysilicon first capacitor plate and polysilicon second capacitor plate, which are inter-digitated with one another and have sidewalls separated from one another by a capacitor dielectric layer, wherein the capacitor dielectric layer and control gate dielectric layer are made of the same material; and
wherein uppermost surfaces of the select gate and first capacitor plate are co-planar with one another.
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Accused Products
Abstract
Some embodiments relate to an integrated circuit (IC). The IC includes a semiconductor substrate including a flash memory region and a capacitor region. A flash memory cell is arranged over the flash memory region and includes a polysilicon select gate arranged between first and second source/drain regions of the flash memory cell. The flash memory cell also includes a control gate arranged alongside the select gate and separated from the select gate by a control gate dielectric layer. A capacitor is arranged over the capacitor region and includes: a polysilicon first capacitor plate and polysilicon second capacitor plate, which are inter-digitated with one another and separated from one another by a capacitor dielectric layer. The capacitor dielectric layer and control gate dielectric layer are made of the same material.
45 Citations
20 Claims
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1. An integrated circuit (IC), comprising:
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a semiconductor substrate including a flash memory region and a capacitor region; a flash memory cell arranged over the flash memory region and including;
a polysilicon select gate arranged between first and second source/drain regions of the flash memory cell, and a control gate arranged alongside the select gate and separated from the select gate by a control gate dielectric layer; anda capacitor arranged over the capacitor region and including;
a polysilicon first capacitor plate and polysilicon second capacitor plate, which are inter-digitated with one another and have sidewalls separated from one another by a capacitor dielectric layer, wherein the capacitor dielectric layer and control gate dielectric layer are made of the same material; andwherein uppermost surfaces of the select gate and first capacitor plate are co-planar with one another. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for manufacturing an embedded flash memory device, the method comprising:
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receiving a semiconductor substrate, which includes a flash region and a capacitor region; forming a first dielectric layer over the flash and capacitor regions of the semiconductor substrate, and forming a first doped polysilicon layer over the first dielectric layer; and removing some portions of the first polysilicon layer and first dielectric layer to establish a select gate over the flash region and a first capacitor plate over the capacitor region, wherein uppermost surfaces of the select gate and the first capacitor plate are co-planar with one another. - View Dependent Claims (12, 13, 14, 15)
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16. An integrated circuit (IC), comprising:
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a semiconductor substrate including a flash memory region and a capacitor region; a flash memory cell arranged over the flash memory region and including;
a polysilicon select gate arranged between first and second source/drain regions of the flash memory cell, and a control gate arranged alongside the select gate and separated from the select gate by a control gate dielectric layer; anda capacitor arranged over the capacitor region and including;
a polysilicon first capacitor plate, a capacitor dielectric layer that conformally and laterally surrounds the polysilicon first capacitor plate, and a polysilicon second capacitor plate that conformally and laterally surrounds the capacitor dielectric layer, wherein at least one of the first and second capacitor plates includes one or more fingers that extend into one or more corresponding sidewall recesses in the other of the first and second capacitor plates such that the first and second capacitor plates are inter-digitated with one another and separated from one another by the capacitor dielectric layer; andwherein uppermost surfaces of the select gate and first capacitor plate are co-planar with one another. - View Dependent Claims (17, 18, 19, 20)
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Specification