Semiconductor device and manufacturing method thereof

• US 9,590,102 B2
• Filed: 04/15/2015
• Issued: 03/07/2017
• Est. Priority Date: 04/15/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kuo-Cheng, Tsai, Ching-Wei, Wang, Chih-Hao, Lien, Wai-Yi
• Primary Examiner(s): Gumedzoe, Peniel M
• Assistant Examiner(s): JOHNSON, CHRISTOPHER A
• Application Number:
  US14/687,815
• Publication Number:
  US 20160308048A1
• Time in Patent Office: 692 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02236 group IV semiconductor
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/02524 Group 14 semiconducting materials
• CPC Class Codes: H01L 21/02529 Silicon carbide
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02645 Seed materials
• CPC Class Codes: H01L 21/7624 using semiconductor on insulator [SOI] technology H01L21/76297 takes precedence; manufacture of integrated circuits on insulating substrates H01L21/84; silicon on sapphire [SOS] technology H01L21/86
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/1604 Amorphous materials
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method for manufacturing a semiconductor device includes forming a fin structure including a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. An isolation insulating layer is formed so that the channel layer of the fin structure protrudes from the isolation insulating layer and a part of or an entirety of the oxide layer is embedded in the isolation insulating layer. A gate structure is formed over the fin structure. A recessed portion is formed by etching a part of the fin structure not covered by the gate structure such that the oxide layer is exposed. A recess is formed in the exposed oxide layer. An epitaxial seed layer in the recess in the oxide layer. An epitaxial layer is formed in and above the recessed portion. The epitaxial layer is in contact with the epitaxial seed layer.

Claims

1. A method for manufacturing a semiconductor device, comprising:

forming a fin structure including a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer;

forming an isolation insulating layer so that the channel layer of the fin structure protrudes from the isolation insulating layer and at least a part of the oxide layer or an entirety of the oxide layer is embedded in the isolation insulating layer;

forming a gate structure over a part of the fin structure and over the isolation insulating layer;

forming a recessed portion by etching a part of the fin structure not covered by the gate structure to expose the oxide layer;

forming a recess in the exposed oxide layer by removing a portion of the exposed oxide layer;

forming a seed layer for epitaxial growth in the recess in the oxide layer; and

forming an epitaxial layer in and above the recessed portion,

wherein the epitaxial layer is in contact with the seed layer.

2. The method of claim 1, wherein the oxide layer includes SiGe oxide.

3. The method of claim 1, wherein the seed layer includes an amorphous semiconductor material or a polycrystalline semiconductor material.

4. The method of claim 1, wherein the seed layer includes amorphous silicon.

5. The method of claim 1, wherein the seed layer is formed by atomic layer deposition.

6. The method of claim 1, wherein the forming a seed layer in the recess includes:

forming a blanket layer of an epitaxial seed material such that the epitaxial seed material is formed over the gate structure, in the recessed portion and in the recess of the oxide layer; and

etching the blanket layer formed over the gate structure and in the recessed portion such that the epitaxial seed material formed in the recess of the oxide layer remains, thereby forming the seed layer.

7. The method of claim 1, wherein a thickness of the seed layer is in a range of 2 nm to 7 nm.

8. The method of claim 1, wherein the epitaxial layer includes multiple epitaxial layers.

9. A method for manufacturing a semiconductor device, comprising:

forming a fin structure including a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer;

forming a seed layer for epitaxial growth over the fin structures having the oxide layer;

forming an isolation insulating layer so that the channel layer of the fin structure protrudes from the isolation insulating layer and at least a part of the oxide layer or an entirety of the oxide layer is embedded in the isolation insulating layer;

forming a gate structure over a part of the fin structure and over the isolation insulating layer;

forming a recessed portion by etching a part of the fin structure not covered by the gate structure to expose the oxide layer and the seed layer formed on a side of the oxide layer; and

forming an epitaxial layer in and above the recessed portion,

wherein the epitaxial layer is in contact with the seed layer formed on a side of the oxide layer.

10. The method of claim 9, wherein the oxide layer includes SiGe oxide.

11. The method of claim 9, wherein the seed layer includes an amorphous semiconductor material or a polycrystalline semiconductor material.

12. The method of claim 9, wherein the seed layer includes amorphous silicon.

13. The method of claim 9, wherein the seed layer is formed by atomic layer deposition.

14. A method for manufacturing a semiconductor device, comprising:

forming a first semiconductor layer over a substrate;

forming a second semiconductor layer over the first semiconductor layer;

forming a fin structure by patterning the second semiconductor layer, the first semiconductor layer and the substrate;

oxidizing the first semiconductor layer into an oxide layer;

forming an isolation insulating layer so that the second semiconductor layer of the fin structure protrudes from the isolation insulating layer and at least a part of the oxide layer or an entirety of the oxide layer is embedded in the isolation insulating layer;

forming a gate structure over a part of the fin structure and over the isolation insulating layer;

after oxidizing the first semiconductor layer into the oxide layer, forming a recessed portion by etching a part of the fin structure not covered by the gate structure to expose the oxide layer; and

forming an epitaxial layer in and above the recessed portion, wherein;

a seed layer for epitaxial growth is formed in contact with the oxide layer before forming the epitaxial layer, and

the epitaxial layer is formed to be in contact with the seed layer.

15. The method of claim 14, wherein the first semiconductor layer is made of Ge or Si_(1-x)Ge_x, and the second semiconductor layer is made of Si or Si_(1-y)Ge_y, where y<

x.

16. The method of claim 15, wherein the seed layer includes an amorphous semiconductor material or a polycrystalline semiconductor material.

17. The method of claim 15, wherein the seed layer is formed after the recessed portion is formed and before the epitaxial layer is formed.

18. The method of claim 17, wherein:

the fin structure extends in a first direction and the gate structure extends in a second direction perpendicular to the first direction, and

the seed layer is formed on side surface of the oxide layer in the first direction.

19. The method of claim 15, wherein the seed layer is formed after the fin structure is formed and before the isolation insulating layer is formed.

20. The method of claim 19, wherein:

the fin structure extends in a first direction and the gate structure extends in a second direction perpendicular to the first direction, and

the seed layer is formed on side surface of the oxide layer in the second direction.