Wafer with SOI structure having a buried insulating multilayer structure and semiconductor device structure

• US 9,590,118 B1
• Filed: 09/14/2015
• Issued: 03/07/2017
• Est. Priority Date: 09/14/2015
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Smith, Elliot John, Beyer, Sven, Chan, Nigel, Hoentschel, Jan
• Primary Examiner(s): Huynh, Andy
• Assistant Examiner(s): Yechuri, Sitaramarao S
• Application Number:
  US14/853,146
• Publication Number:
  US 20170077314A1
• Time in Patent Office: 540 Days
• Field of Search: 257/324
• US Class Current: 1/1
• CPC Class Codes: H01L 21/326 Application of electric currents or fields, e.g. for electroforming H01L21/20 - H01L21/288 and H01L21/302 - H01L21/324 take precedence
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7923 Programmable transistors with more than two possible different levels of programmation

Abstract

The present disclosure provides, in a first aspect, a semiconductor device structure, including an SOI substrate comprising a semiconductor base substrate, a buried insulating structure formed on the semiconductor base substrate and a semiconductor film formed on the buried insulating structure, wherein the buried insulating structure comprises a multilayer stack having a nitride layer interposed between two oxide layers. The semiconductor device structure further includes a semiconductor device formed in and above an active region of the SOI substrate, and a back bias contact which is electrically connected to the semiconductor base substrate below the semiconductor device.

Claims

1. A semiconductor device structure, comprising:

an SOI substrate comprising a semiconductor base substrate material, a buried insulating structure formed on said base substrate material, and a semiconductor film formed on said buried insulating structure, wherein said buried insulating structure comprises a multilayer stack having a nitride layer interposed between two oxide layers;

a semiconductor device formed in and above an active region of said SOI substrate, comprising;

a gate structure;

raised source/drain regions located at opposing sides of said gate structure; and

a silicide contact region defined in said base substrate material below said semiconductor device;

a nitride material layer disposed above said semiconductor device and at least a portion of said silicide contact region,

a contact dielectric disposed above said nitride material layer, and

a back bias contact at least partially disposed in said contact dielectric and being electrically connected to said silicide contact region.

2. The semiconductor device structure of claim 1, wherein said gate structure comprises a gate dielectric disposed above said SOI substrate, said gate dielectric comprising a high-k material.

3. The semiconductor device structure of claim 1, wherein said semiconductor device structure is laterally enclosed by a shallow trench isolation (STI) structure.

4. A method of forming a semiconductor device structure, the method comprising:

providing a wafer with an SOI structure having a buried insulating multilayer structure interposed between an active semiconductor layer and a base substrate material;

forming a gate structure above said active semiconductor layer;

forming raised source/drain regions at opposing sides of said gate structure;

forming a back bias contact structure for contacting said base substrate material below said gate structure, said back bias contact structure being electrically insulated from said active semiconductor layer, wherein forming said back bias contact structure comprises partially removing said active semiconductor layer and said buried insulating multilayer structure for exposing a surface region of said base substrate material adjacent to said gate structure and performing a salicidation process for forming a self-aligned silicide contact region for contacting said exposed surface region of said base substrate material;

depositing a nitride material layer above said gate structure after forming said silicide contact region, and

depositing a contact dielectric over said deposited nitride material layer.

5. The method of claim 4, wherein said buried insulating multilayer structure comprises a nitride material layer interposed between oxide material layers.

6. The method of claim 4, wherein depositing said nitride material layer comprises performing a chemical vapor deposition (CVD) process.

7. The method of claim 4, further comprising forming a masking pattern on said deposited contact dielectric and etching a contact trench into said contact dielectric in accordance with said masking pattern for at least partially exposing said silicide contact region and filling said contact trench with a contact forming material.

8. The method of claim 4, wherein said self-aligned silicide contact region is formed when forming a silicide gate contact region for contacting said gate structure.

9. The method of claim 4, further comprising forming a sidewall spacer extension structure on said raised source/drain regions at an upper portion of said gate structure.

10. The method of claim 9, wherein said sidewall spacer extension structure is formed by depositing one of a nitride material and an oxide material over said semiconductor device structure and anisotropically etching said deposited material so as to form said sidewall spacer extension structure.

11. The method of claim 9, wherein said gate structure comprises a gate cap formed on a gate electrode material, said gate cap being removed to expose an upper surface of said gate electrode material when said sidewall spacer extension structure is formed.

12. The method of claim 4, further comprising applying a voltage pulse having a peak value of one of more than about 5 V and less than about −

5 V to said back bias contact for creating a stable shift in a threshold voltage (Vt) of a semiconductor device comprising said gate structure and said raised source/drain regions.

13. The method of claim 12, further comprising applying a voltage of an absolute value of about at most 3 V to said back bias contact for tuning said threshold voltage (Vt).

14. The method of claim 4, further comprising forming a second gate structure above said active semiconductor layer, and forming a shallow trench isolation between said gate structure and said second gate structure, wherein said shallow trench isolation extends to said base substrate material and ends on an upper surface of said base semiconductor material.

15. The method of claim 4, further comprising forming a third gate structure above said active semiconductor layer, forming a trench isolation between said gate structure and said third gate structure, wherein said shallow trench isolation extends into said base substrate material to separate a first base substrate region below said gate structure from a second substrate region below said third gate structure, and forming a second back bias contact by exposing an upper surface region of said second base substrate region and forming a silicide contact region on said exposed upper surface of said second base substrate region for contacting said second base substrate region.