Partial reconfiguration of programmable devices

• US 9,590,635 B1
• Filed: 12/03/2015
• Issued: 03/07/2017
• Est. Priority Date: 12/03/2015
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Sengupta, Shayan
• Primary Examiner(s): Crawford, Jason M
• Application Number:
  US14/958,303
• Time in Patent Office: 460 Days
• Field of Search: 326 37- 41, 326/47, 710313-315
• US Class Current: 1/1
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration

Abstract

Techniques and mechanisms disclosed herein provide a partial reconfiguration bitstream for a region of configurable logic of a programmable logic device over a communications interface such as the Peripheral Component Interconnect Express (PCIe) protocol.

Claims

1. A bridge circuit of a programmable logic device (PLD) to:

receive a first configuration data from a communications interface, the first configuration data indicating states of configurable elements of a region of configurable logic of the PLD to implement a first functionality, the bridge circuit to freeze inputs and outputs of the region of the configurable logic, and the bridge circuit to provide bits of the first configuration data to a control block of the PLD to configure the configurable elements after freezing the inputs and outputs.

2. The bridge circuit of claim 1, wherein the bridge circuit is to adjust a clock signal used by the control block based on a rate of the first configuration data being provided over the communications interface.

3. The bridge circuit of claim 1, wherein the communications interface conforms to a Peripheral Component Interconnect Express (PCIe) protocol.

4. The bridge circuit of claim 1, wherein the configurable elements indicated in the first configuration data correspond to a subset of configuration elements of the configurable logic of the PLD.

5. The bridge circuit of claim 1, wherein the bridge circuit is further to receive a second configuration data from the communications interface, the second configuration data indicating states of the configurable elements of the region to implement a second functionality.

6. The bridge circuit of claim 1, wherein the bridge circuit is further to provide an identifier corresponding to the region to the control block.

7. The bridge circuit of claim 1, wherein the bridge circuit is further to extract bits from the first configuration data to provide a partial reconfiguration bitstream corresponding to the configuration elements of the region to the control block.

8. The bridge circuit of claim 1, wherein the bridge circuit is further to receive status data from the control block and provide the status data on the communications interface to a host device.

9. A method for partial reconfiguration of a programmable logic device (PLD), the method comprising:

receiving, by a bridge circuit of the PLD, from a communication interface providing communications between the PLD and a host device, an indication that a portion of configurable logic of the PLD is to be reconfigured;

freezing, by the bridge circuit, inputs and outputs of the portion of the configurable logic of the PLD;

receiving, by the bridge circuit, data providing a partial reconfiguration bitstream for the portion of the configurable logic of the PLD that is to be reconfigured; and

providing, by the bridge circuit, the partial reconfiguration bitstream for the portion of the configurable logic of the PLD to a control block for reconfiguring the portion of the configurable logic.

10. The method of claim 9, further comprising:

reconfiguring configurable elements of the portion of the configurable logic of the PLD based on the partial reconfiguration bitstream.

11. The method of claim 10, wherein the configurable elements indicated in the partial reconfiguration bitstream correspond to a subset of configuration elements of the configurable logic of the PLD.

12. The method of claim 9, further comprising:

adjusting a frequency of a clock signal used by the control block based on a rate of receiving the data providing the partial reconfiguration bitstream.

13. The method of claim 9, wherein the communications interface conforms to a Peripheral Component Interconnect Express (PCIe) protocol.

14. The method of claim 9, further comprising:

extracting bits from the data to provide the partial reconfiguration bitstream.

15. A system comprising:

a bridge circuit to receive configuration data from a host device, the configuration data indicating states of configurable elements of a region of configurable logic to implement a first functionality, the bridge circuit to freeze inputs and outputs of the region of the configurable logic, and

a control circuit to receive a bitstream from the configuration data to configure the configurable elements of the region, bits in the bitstream corresponding to the states of the configuration elements of the region of the configurable logic.

16. The system of claim 15, wherein the bridge circuit is to adjust a clock signal used by the control circuit based on a rate of the configuration data being received.

17. The system of claim 15, wherein the configurable elements indicated in the configuration data correspond to a subset of configuration elements of the configurable logic of a PLD including the bridge circuit and the control circuit.

18. The system of claim 15, wherein the bridge circuit communicates with the host device with a communications interface conforming to a Peripheral Component Interconnect Express (PCIe) protocol.

19. The system of claim 18, wherein the bridge circuit is further to receive status data from the control circuit and provide the status data on the communications interface to the host device.

20. The system of claim 15, wherein the bridge circuit is further to provide an identifier corresponding to the region to the control circuit.