High-speed programmable frequency divider with 50% output duty cycle

• US 9,590,637 B1
• Filed: 08/28/2015
• Issued: 03/07/2017
• Est. Priority Date: 08/28/2015
• Status: Active Grant

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Lau, Pak-Kim, Chu, Min
• Primary Examiner(s): Nguyen, Long
• Application Number:
  US14/839,817
• Time in Patent Office: 557 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H03K 21/10 comprising logic circuits
• CPC Class Codes: H03K 23/40 Gating or clocking signals applied to all stages, i.e. synchronous counters H03K23/74 - H03K23/84 take precedence
• CPC Class Codes: H03K 23/66 with a variable counting base, e.g. by presetting or by adding or suppressing pulses

Abstract

A frequency divider includes a multiplexer having a first input terminal coupled to receive a first value M and a second input terminal for receiving a second value that is M+LSB, the multiplexer is configured to alternately output the first value M and the second value. The frequency divider includes a multi-modulus divider coupled to the multiplexer for receiving the output of the multiplexer, the multi-modulus divider operable to alternately generate an output pulse at M input clock cycles and at M+LSB clock cycles. A divide-by-two counter having an input coupled to the output of the multi-modulus divider, is operable to divide the output of the multi-modulus divider to generate a divided clock signal having a frequency of N, where N is equal to 2M+LSB. Duty cycle correction logic is coupled to the output of the divide-by-two counter and is configured to correct the duty cycle of the divided clock signal to a fifty percent duty cycle when N is odd.

Claims

1. An integrated circuit device comprising:

a multiplexer having a first input terminal coupled to receive a first integer value (M) and a second input terminal for receiving a second integer value that is M plus a least significant bit (LSB), the multiplexer configured to alternately output M and the second integer value;

a multi-modulus divider coupled to the multiplexer for receiving the output of the multiplexer and having a clock input for receiving a clock signal, the multi-modulus divider operable to alternately generate an output pulse at M input clock cycles and at M+LSB clock cycles;

a divide-by-two counter having an input coupled to the output of the multi-modulus divider, the divide-by-two counter operable to divide the output of the multi-modulus divider to generate a divided clock signal having a frequency equal to 2M+LSB; and

duty cycle correction logic coupled to the output of the divide by two counter, the duty cycle correction logic configured to correct the duty cycle of the divided clock signal to a fifty percent duty cycle when the LSB is odd.

2. The integrated circuit device of claim 1 further comprising an adder having an output coupled to the multiplexer, a first input for receiving M and a second input for receiving the LSB, the adder operable to add M and the LSB.

3. The integrated circuit device of claim 1 wherein a select terminal of the multiplexer is coupled to the output of the divide-by-two counter for receiving the divided clock signal.

4. The integrated circuit device of claim 3 wherein the divided clock signal has an output that is high for M+1 cycles and low for M cycles when the frequency is odd.

5. The integrated circuit device of claim 3 wherein the divide-by-two counter further comprises a flip-flop and an inverter coupled to the flip flop, the inverter having an input coupled to receive the divided clock signal and having an output coupled to an input of the flip-flop, the flip-flop having a clock input coupled to receive the output of the multi-modulus divider, the flip-flop operable to generate the divided clock signal.

6. The integrated circuit device of claim 3 wherein the duty cycle correction logic further comprises an OR gate, a first flip-flop and a second flip-flop, the first flip-flop coupled to the second flip-flop, wherein the first flip-flop is clocked by the input clock signal and the second flip-flop is clocked by the complement of the input clock signal and further wherein the output of the first flip-flop is coupled to a first input of the OR gate and the output of the second flip-flop is coupled to a second input of the OR gate.

7. The integrated circuit device of claim 3 wherein the duty cycle correction logic further comprises an AND gate, a first flip-flop and a second flip-flop, the first flip-flop coupled to the second flip-flop, wherein the first flip-flop is clocked by the input clock signal and the second flip-flop is clocked by the complement of the input clock signal.

8. The integrated circuit device of claim 7 wherein the output of the first flip-flop is coupled to a first input of the AND gate and the complement of the output of the first flip-flop is coupled to an input of the second flip-flop, and wherein the complement of the output of the second flip-flop is coupled to the second input of the AND gate.

9. A method comprising:

alternately dividing an input clock signal by a first divisor having a first integer value (M) M and a second divisor having a value of M plus a least significant bit (LSB) to alternate periodically between generating an output pulse at M input clock cycles and M+LSB input clock cycles;

dividing the generated output pulse using a divide-by-two counter to generate a divided clock signal having a frequency equal to 2M+LSB; and

correcting the duty cycle of the divided clock signal when the LSB is odd to generate a corrected divided clock signal having a fifty percent duty cycle.

10. The method of claim 9 wherein the divided clock signal has an output that is high for M+1 cycles and low for M cycles when the LSB is odd.

11. The method of claim 9 wherein the correcting the duty cycle further comprises correcting the duty cycle using duty cycle correction logic that includes a first flip-flop and a second flip-flop that are clocked at half of a clock cycle apart from each other, and that includes an AND gate coupled to the output of the first flip-flop and to the complement of the output of the second flip-flop.

12. A frequency divider comprising:

an adder having a first input for receiving a first integer value (M) and a second input for receiving a least significant bit (LSB), the adder operable to generate a second integer value at the output of the adder that is the sum of M and the LSB;

a multiplexer having a first input terminal coupled to receive M and having a second input terminal electrically coupled to the output of the adder for receiving the second integer value, the multiplexer configured to alternately output M and the second integer value;

a multi-modulus divider coupled to the multiplexer for receiving the output of the multiplexer and having a clock input for receiving a clock signal, the multi-modulus divider operable to alternately generate an output pulse at M input clock cycles and at M+LSB clock cycles;

a divide-by-two counter having an input coupled to the output of the multi-modulus divider, the divide-by-two counter operable to divide the output of the multi-modulus divider to generate a divided clock signal having a frequency equal to 2M+LSB; and

duty cycle correction logic coupled to the output of the divide by two counter, the duty cycle correction logic configured to correct the duty cycle of the divided clock signal to a fifty percent duty cycle when the LSB is odd.

13. The frequency divider of claim 12 wherein a select terminal of the multiplexer is coupled to the output of the divide-by-two counter for controlling the operation of the multiplexer.

14. The frequency divider of claim 12 wherein the divided clock signal has an output that is high for M+1 cycles and low for M cycles when the LSB is odd.

15. The frequency divider of claim 12 wherein the divide-by-two counter further comprises a flip-flop and an inverter coupled to the flip flop, the inverter having an input coupled to receive the divided clock signal and having an output coupled to an input of the flip-flop, the flip-flop having a clock input coupled to receive the output of the multi-modulus divider, the flip-flop operable to generate the divided clock signal.

16. The frequency divider of claim 12 wherein the duty cycle correction logic further comprises an OR gate, a first flip-flop and a second flip-flop, the first flip-flop coupled to the second flip-flop, wherein the first flip-flop is clocked by the input clock signal and the second flip-flop is clocked by the complement of the input clock signal and further wherein the output of the first flip-flop is coupled to a first input of the OR gate and the output of the second flip-flop is coupled to a second input of the OR gate.

17. The frequency divider of claim 12 wherein the duty cycle correction logic further comprises an AND gate, a first flip-flop and a second flip-flop, the first flip-flop coupled to the second flip-flop, wherein the first flip-flop is clocked by the input clock signal and the second flip-flop is clocked by the complement of the input clock signal.

18. The frequency divider of claim 17 wherein the output of the first flip-flop is coupled to a first input of the AND gate and the complement of the output of the first flip-flop is coupled to an input of the second flip-flop, and wherein the complement of the output of the second flip-flop is coupled to the second input of the AND gate.