Compact electronics test system having user programmable device interfaces and on-board functions adapted for use in proximity to a radiation field

• US 9,594,117 B2
• Filed: 11/24/2014
• Issued: 03/14/2017
• Est. Priority Date: 11/22/2013
• Status: Active Grant

• Current Assignee: the united states of america as represented by the secretary of the navy
• Original Assignee: the united states of america as represented by the secretary of the navy
• Inventors: Duncan, Adam, Gadlage, Matthew
• Primary Examiner(s): Nguyen, Tung X
• Application Number:
  US14/551,418
• Publication Number:
  US 20150145548A1
• Time in Patent Office: 841 Days
• US Class Current: 1/1
• CPC Class Codes: G01R 1/18 Screening arrangements against electric or magnetic fields, e.g. against earth's field
• CPC Class Codes: G01R 3/00 Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments , e.g. of probe tips
• CPC Class Codes: G01R 31/31728 Optical aspects, e.g. opto-electronics used for testing, optical signal transmission for testing electronic circuits, electro-optic components to be tested in combination with electronic circuits, measuring light emission of digital circuits probes having electro-optic elements G01R1/071; electro-optic sampling for oscilloscopes G01R13/347; contactless testing of individual semiconductor devices by optical means G01R31/2656
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: G01R 31/31914 Portable Testers
• CPC Class Codes: Y10T 29/49002 Electrical device making

Abstract

Various apparatus and method s associated with a compact electronics test system having user programmable device interfaces and on-board functions adapted for use in various environments are provided. Exemplary embodiments can include a variety of apparatuses and method s to realize an advanced field programmable gate array adapted to perform functional tests on digital electronics within an exemplary 48-pin DIP footprint. One aspect of the invention can include a testing device comprised of components to produce a product that is inexpensive and consumable. A small size of an exemplary embodiment of the invention further allows for desirable shielding to be placed around a highly portable and highly programmable and adaptable testing device in order to protect it from external dangers found in harsh environments (e.g., high levels of radiation when operating in space, etc).

Claims

1. A method comprising:

a first test structure comprising at least one first interface section and a second interface section, wherein said second interface section comprises an integrated circuit interface section comprising a plurality of programmable input and output elements, wherein said integrated circuit interface section is adapted to removably and electrically connect or release one or more said input and output elements with one or more input and output elements of a device under test (DUT), receive inputs and outputs from said DUT, process said inputs and outputs, and output processed data;

a second test structure comprising;

a third interface section adapted to selectively and removably electrically couple with said first interface section of said first structure;

a power module adapted to modulate incoming power to different voltages from a power supply either on said second test structure or coupled with said second test structure, said power module supplies said different voltages to sections of said first and section test structure comprising one or more said plurality of programmable input and output elements through said first test structure via said third interface section to said first interface section;

a user selectable voltage switch adapted to enable said user to select between said different voltages by manipulating said switch in different switch selection configurations;

a programmable read only memory (PROM) adapted to store a first plurality of machine readable instructions and a first plurality of field programmable gate array (FPGA) configuration settings;

a FPGA adapted to perform a plurality of FPGA operations comprising controlling said DUT and said programmable input and output elements through said third interface section, said FPGA is configured to couple with said PROM and receive said first plurality of machine readable instructions in an initial testing configuration and said first plurality of FPGA configuration settings, wherein said FPGA is further configured to create and store a second plurality of FPGA configuration settings on said PROM for later reload of said FPGA from said PROM, wherein said FPGA is also configured to selectively program said power module to select one of said different voltages and selectively configure and program one or more of said plurality of programmable input and output elements based on said first or second plurality of machine readable instructions, wherein said first and second plurality of machine readable instructions are configured to either reconfigure programmable logic elements within said FPGA or be executed by different programmable logic elements within said FPGA to perform said plurality of FPGA operations;

an initial configuration load switch configured to transfer a copy of said first plurality of machine readable instructions to said FPGA to operate said FPGA in said first testing configuration operable to perform a first plurality of testing operations on said DUT;

a timing signal generation section operable to supply one or different timing signals to said FPGA;

a programming cable connection coupled with said FPGA adapted to electrically couple with a programming cable configured for receiving and conveying said first plurality of machine readable instructions or a second plurality of machine readable instructions to said FPGA;

a plurality of light emitting diodes (LED) coupled with said FPGA adapted to indicate user programmable indication criteria settings associated with execution of said first or second plurality of machine readable instructions by said FPGA by outputting a different light emission associated with predetermined said indication criteria that have been met; and

a communication protocol section adapted to transmit data from said FPGA through a communication signal data interface adaptor to a computer adapted to analyze said data.

2. The method as in claim 1, further comprising a third test structure configured to selectively receive and release said second test structure and further electrically interface said second test structure with said first test structure.

3. The method as in claim 1, wherein said first test structure comprises an integrated circuit package receiving section adapted to receive a DUT comprising a 48-pin dual-inline package (DIP) system, wherein said communication signal data interface comprises an RS232 adapter.

4. The method as in claim 3, wherein said integrated circuit package receiving section and said 48-pin DIP further comprises a shielding section adapted to prevent or mitigate damage from a radiation environment above a radiation threshold or heat exposure above a thermal threshold.

5. The method as in claim 3, further comprising a shield case adapted to encase said 48-pin DIP with a radiation shielding material.

6. The method as in claim 1, wherein said second test structure further comprises said power supply on said second test structure configured to supply power to said power module.

7. The method as in claim 1, wherein said FPGA is further configured by said first or second plurality of machine readable instructions to multiply, scale, or adjust said timing signals supplied to said FPGA from said timing section.

8. The method as in claim 3, wherein said 48-pin DIP comprises a plurality of input and outputs (I/O) configured to be grounds, one I/O configured to be a voltage input I/O, one I/O configured to be a receive I/O, one I/O configured to be a transmit I/O, and forty I/Os configured to be programmable I/Os.

9. The method as in claim 3, wherein said user selectable voltage switch comprises a supply voltage VDD I/O switch configured to enable said user to select one of said different voltages to one or more pins of said 48-pin DIP.

10. The method as in claim 1, wherein said second test structure is formed with an aperture in said test structure passing through said second test structure, said first test structure is substantially positioned over said aperture so as said DUT is entirely over said aperture, said aperture is sized to permit radiation to be passed through said aperture without directly impacting said second test structure.

11. A method comprising:

a first test structure comprising an adapter board comprising a first electrical signal interface configured with structures for selectively retaining and interfacing with a first plurality of electrical signal input and output (I/O) interface elements, a third electrical signal interface configured with for selectively retaining and interfacing with a second plurality of electrical signal I/O interface elements, a first power supply interface and bus, and a communication interface and bus;

a second test structure comprising a device under test (DUT) board including a DUT interface structure comprising a plurality of programmable DUT I/O elements and a retaining structure adapted to selectively receive, retain, and interface with a plurality of DUT interface elements of said DUT, a second electrical signal interface comprising said first plurality of electrical signal I/O elements removeably coupled with said first electrical signal interface, a DUT board bus structure configured to interface said DUT interface structure with said first test structure interface;

a third test structure comprising;

a fourth electrical signal interface comprising said third plurality of electrical signal I/O elements coupled to a third test structure bus structure selectively coupled with said third electrical signal interface;

a power module coupled with said third test structure bus adapted to modulate incoming power to selectively supply one of a plurality of different voltages to said plurality of programmable DUT I/O elements through said fourth electrical signal interface;

a user selectable voltage switch coupled with said third test structure bus adapted to enable said user to select said one of a plurality of different voltages by manipulating said switch in different switch selection configurations;

a programmable read only memory (PROM) coupled with said third test structure bus adapted to store a first plurality of machine readable instructions and a first plurality of field programmable gate array (FPGA) configuration settings;

a FPGA coupled with said third test structure bus adapted to perform a plurality of FPGA operations comprising controlling said DUT through said fourth electrical signal interface by selectively switching, configuring, or coupling with said programmable DUT I/O elements through said third interface section based on said first plurality of machine readable instructions or a second plurality of machine readable instructions loaded on said FPGA operable to operate or configure programmable logic blocks on said FPGA, said FPGA is configured to selectively couple with said PROM and receive said first plurality of machine readable instructions in an initial testing configuration and said first plurality of FPGA configuration settings, wherein said FPGA is further configured to receive or create a second plurality of FPGA configuration settings, said first or second plurality of machine readable instructions further include instructions operable to configure said FPGA to store said first plurality of machine readable instructions, said second plurality of machine readable instructions, said first plurality of FPGA configuration settings, or said second plurality of FPGA configuration settings on said PROM for later reload or configuration of said FPGA from said PROM, wherein said FPGA is also configured to selectively program said power module to select said one of said plurality of different voltages and selectively configure and program one or more of said plurality of programmable DUT I/O elements based on said first or second plurality of machine readable instructions, wherein said first and second plurality of machine readable instructions are configured to either reconfigure programmable logic elements within said FPGA or be executed by different programmable logic elements within said FPGA to perform said plurality of FPGA operations;

an initial configuration load switch coupled with said third test structure bus configured to transfer a copy of said first plurality of machine readable instructions to said FPGA to operate said FPGA in said first testing configuration operable to perform a first plurality of testing operations on said DUT;

a timing signal generation section coupled with said third test structure bus operable to supply one or different timing signals to said FPGA;

a programming cable connection coupled with said FPGA adapted to electrically couple with a programming cable configured for receiving and conveying said first plurality of machine readable instructions or said second plurality of machine readable instructions to said FPGA;

a plurality of light emitting diodes (LED) coupled with said FPGA through coupled with said third test structure bus adapted to indicate user programmable indication criteria settings associated with execution of said first or second plurality of machine readable instructions by said FPGA by outputting a different light emission associated with predetermined said indication criteria that have been met; and

a communication protocol section adapted to transmit DUT test or operation data from said FPGA through said fourth electrical signal interface with said communication interface to a computer adapted to analyze said data.

12. The method as in claim 11, wherein said DUT interface structure comprises an integrated circuit package receiving section adapted to receive a DUT comprising a 48-pin dual-inline package (DIP) system, wherein said communication interface comprises an RS232 adapter.

13. The method as in claim 12, wherein said integrated circuit package receiving section and said 48-pin DIP further comprises a shielding section adapted to prevent or mitigate damage from a radiation environment above a radiation threshold or heat exposure above a thermal threshold.

14. The method as in claim 12, further comprising a shield case adapted to encase said 48-pin DIP with a radiation shielding material.

15. The method as in claim 11, wherein said FPGA is further configured by said first or second plurality of machine readable instructions to multiply, scale, or adjust said timing signals supplied to said FPGA from said timing section.

16. The method as in claim 12, wherein said 48-pin DIP comprises a plurality of I/O elements configured to be grounds, one I/O configured to be a voltage input I/O, one I/O configured to be a receive I/O, one I/O configured to be a transmit I/O, and forty I/Os configured to be programmable I/Os.

17. The method as in claim 12, wherein said user selectable voltage switch comprises a supply voltage VDD I/O switch configured to enable said user to select one of said different voltages to one or more I/O elements or pins of said 48-pin DIP.

18. The method as in claim 11, wherein said adapter board further comprises an aperture, said first electrical signal interface is disposed outside and in proximity with said aperture, wherein said DUT interface structure is formed and positioned to position said DUT over said aperture in said first test structure.

19. A method of manufacturing an electronic method comprising:

providing a device under test (DUT) board;

providing a power supply adapted to supply power to a 48-pin dual-inline package (DIP) coupled with said DUT board; and

providing said 48-pin DIP comprising;

a power module adapted to modulate incoming power from said power supply to different voltages adapted to regulate voltage to 1.2V, 1.5V, 1.8V, 2.5V, or 3.3V;

a user selectable voltage switch adapted to enable the user to select between said voltages;

a PROM;

a FPGA adapted to control I/Os on said 48-pin DIP;

an 80 MHz oscillator adapted to supply timing to said FPGA;

a programming cable connection adapted to accept a programming cable capable of sending programming instructions to said FPGA;

a plurality of LEDs adapted to indicate user programmable indication criteria;

a communication protocol adapted to transmit data from said FPGA through a RS232 adaptor to a computer adapted to analyze said data.

20. The method of claim 19, wherein said coupling between said 48-pin DIP and said DUT board comprises a zero insertion force (ZIF) connection.

21. The method of claim 19, wherein a coaxial cable is used in said providing power step to provide power to said 48-pin DIP.

22. A method of testing a digital electronic device comprising:

releasably coupling receive and transmit input/outputs (I/O) of a device under test (DUT) board with a DUT comprising a 48-pin dual-inline package (DIP);

applying a voltage to said DUT via said DUT board from a tester assembly comprising a field programmable gate array (FPGA), a programmable read only memory (PROM), wherein a programmable read only memory (PROM) is adapted to write stored data into a FPGA comprising FPGA setting data and a plurality of machine readable instructions operable to program programmable logic blocks on said FPGA to perform a plurality of FPGA operations comprising a first plurality of test operations configured to control and operate said DUT, wherein said tester is adapted to receive commands to initialize test sequence, wherein said tester is adapted to read said DUT to test for errors or bad data within said DUT, wherein said tester is adapted to store said error data in a memory device or transmit to said computer,

outputting data associated with said plurality of FPGA operations and data associated with DUT output from to a computer adapted to analyze said data associated with said DUT output and said plurality of FPGA operations and producing a test report output via an output device comprising one of a display, a printer, or a stored data file on a machine readable recording medium.

23. A method of manufacturing a method comprising:

providing a first test structure comprising at least one first interface section and a second interface section, wherein said second interface section comprises an integrated circuit interface section comprising a plurality of programmable input and output elements, wherein said integrated circuit interface section is adapted to removably and electrically connect or release one or more said input and output elements with one or more input and output elements of a device under test (DUT), receive inputs and outputs from said DUT, process said inputs and outputs, and output processed data;

providing a second test structure comprising;

a third interface section adapted to selectively and removably electrically couple with said first interface section of said first structure;

a power module adapted to modulate incoming power to different voltages from a power supply either on said second test structure or coupled with said second test structure, said power module supplies said different voltages to sections of said first and section test structure comprising one or more said plurality of programmable input and output elements through said first test structure via said third interface section to said first interface section;

a user selectable voltage switch adapted to enable said user to select between said different voltages by manipulating said switch in different switch selection configurations;

a programmable read only memory (PROM) adapted to store a first plurality of machine readable instructions and a first plurality of field programmable gate array (FPGA) configuration settings;

a FPGA adapted to perform a plurality of FPGA operations comprising controlling said DUT and said programmable input and output elements through said third interface section, said FPGA is configured to couple with said PROM and receive said first plurality of machine readable instructions in an initial testing configuration and said first plurality of FPGA configuration settings, wherein said FPGA is further configured to create and store a second plurality of FPGA configuration settings on said PROM for later reload of said FPGA from said PROM, wherein said FPGA is also configured to selectively program said power module to select one of said different voltages and selectively configure and program one or more of said plurality of programmable input and output elements based on said first or second plurality of machine readable instructions, wherein said first and second plurality of machine readable instructions are configured to either reconfigure programmable logic elements within said FPGA or be executed by different programmable logic elements within said FPGA to perform said plurality of FPGA operations;

an initial configuration load switch configured to transfer a copy of said first plurality of machine readable instructions to said FPGA to operate said FPGA in said first testing configuration operable to perform a first plurality of testing operations on said DUT;

a timing signal generation section operable to supply one or different timing signals to said FPGA;

a programming cable connection coupled with said FPGA adapted to electrically couple with a programming cable configured for receiving and conveying said first plurality of machine readable instructions or a second plurality of machine readable instructions to said FPGA;

a plurality of light emitting diodes (LED) coupled with said FPGA adapted to indicate user programmable indication criteria settings associated with execution of said first or second plurality of machine readable instructions by said FPGA by outputting a different light emission associated with predetermined said indication criteria that have been met; and

a communication protocol section adapted to transmit data from said FPGA through a communication signal data interface adaptor to a computer adapted to analyze said data;

wherein said second test structure size and design of components placed on said first test structure is determined based on a plurality of factors comprising reducing said second test structure size to substantially reduce said second test structure area exposure to a radiation source and reduction of said second test structure'"'"'s size with respect to said first test structure'"'"'s size to a predetermined percentage, extension beyond, or ratio with respect to said first test structure size.

24. The method as in claim 23, further comprising a third test structure configured to selectively receive and release said second test structure and further electrically interface said second test structure with said first test structure.

25. The method as in claim 23, wherein said first test structure comprises an integrated circuit package receiving section adapted to receive a DUT comprising a 48-pin dual-inline package (DIP) system, wherein said communication signal data interface comprises an RS232 adapter.

26. The method as in claim 25, wherein said integrated circuit package receiving section and said 48-pin DIP further comprises a shielding section adapted to prevent or mitigate damage from a radiation environment above a radiation threshold or heat exposure above a thermal threshold.

27. The method as in claim 25, further comprising a shield case adapted to encase said 48-pin DIP with an electromagnetic radiation shielding material.

28. The method as in claim 23, wherein said second test structure further comprises said power supply on said second test structure configured to supply power to said power module.

29. The method as in claim 23, wherein said FPGA is further configured by said first or second plurality of machine readable instructions to multiply, scale, or adjust said timing signals supplied to said FPGA from said timing section.

30. The method as in claim 25, wherein said 48-pin DIP comprises a plurality of input and outputs (I/O) configured to be grounds, one I/O configured to be a voltage input I/O, one I/O configured to be a receive I/O, one I/O configured to be a transmit I/O, and forty I/Os configured to be programmable I/Os.

31. The method as in claim 25, wherein said user selectable voltage switch comprises a supply voltage VDD I/O switch configured to enable said user to select one of said different voltages to one or more pins of said 48-pin DIP.

32. The method as in claim 23, wherein said second test structure is formed with an aperture in said test structure passing through said second test structure, said first test structure is substantially positioned over said aperture so as said DUT is entirely over said aperture, said aperture is sized to permit radiation to be passed through said aperture without directly impacting said second test structure.

33. A method of manufacturing a method comprising:

providing a first test structure comprising an adapter board comprising a first electrical signal interface configured with structures for selectively retaining and interfacing with a first plurality of electrical signal input and output (I/O) interface elements, a third electrical signal interface configured with for selectively retaining and interfacing with a second plurality of electrical signal I/O interface elements, a first power supply interface and bus, and a communication interface and bus;

providing a second test structure comprising a device under test (DUT) board including a DUT interface structure comprising a plurality of programmable DUT I/O elements and a retaining structure adapted to selectively receive, retain, and interface with a plurality of DUT interface elements of said DUT, a second electrical signal interface comprising said first plurality of electrical signal I/O elements removeably coupled with said first electrical signal interface, a DUT board bus structure configured to interface said DUT interface structure with said first test structure interface;

providing a third test structure comprising;

a fourth electrical signal interface comprising said third plurality of electrical signal I/O elements coupled to a third test structure bus structure selectively coupled with said third electrical signal interface;

a power module coupled with said third test structure bus adapted to modulate incoming power to selectively supply one of a plurality of different voltages to said plurality of programmable DUT I/O elements through said fourth electrical signal interface;

a user selectable voltage switch coupled with said third test structure bus adapted to enable said user to select said one of a plurality of different voltages by manipulating said switch in different switch selection configurations;

a programmable read only memory (PROM) coupled with said third test structure bus adapted to store a first plurality of machine readable instructions and a first plurality of field programmable gate array (FPGA) configuration settings;

a FPGA coupled with said third test structure bus adapted to perform a plurality of FPGA operations comprising controlling said DUT through said fourth electrical signal interface by selectively switching, configuring, or coupling with said programmable DUT I/O elements through said third interface section based on said first plurality of machine readable instructions or a second plurality of machine readable instructions loaded on said FPGA operable to operate or configure programmable logic blocks on said FPGA, said FPGA is configured to selectively couple with said PROM and receive said first plurality of machine readable instructions in an initial testing configuration and said first plurality of FPGA configuration settings, wherein said FPGA is further configured to receive or create a second plurality of FPGA configuration settings, said first or second plurality of machine readable instructions further include instructions operable to configure said FPGA to store said first plurality of machine readable instructions, said second plurality of machine readable instructions, said first plurality of FPGA configuration settings, or said second plurality of FPGA configuration settings on said PROM for later reload or configuration of said FPGA from said PROM, wherein said FPGA is also configured to selectively program said power module to select said one of said plurality of different voltages and selectively configure and program one or more of said plurality of programmable DUT I/O elements based on said first or second plurality of machine readable instructions, wherein said first and second plurality of machine readable instructions are configured to either reconfigure programmable logic elements within said FPGA or be executed by different programmable logic elements within said FPGA to perform said plurality of FPGA operations;

an initial configuration load switch coupled with said third test structure bus configured to transfer a copy of said first plurality of machine readable instructions to said FPGA to operate said FPGA in said first testing configuration operable to perform a first plurality of testing operations on said DUT;

a timing signal generation section coupled with said third test structure bus operable to supply one or different timing signals to said FPGA;

a programming cable connection coupled with said FPGA adapted to electrically couple with a programming cable configured for receiving and conveying said first plurality of machine readable instructions or said second plurality of machine readable instructions to said FPGA;

a plurality of light emitting diodes (LED) coupled with said FPGA through coupled with said third test structure bus adapted to indicate user programmable indication criteria settings associated with execution of said first or second plurality of machine readable instructions by said FPGA by outputting a different light emission associated with predetermined said indication criteria that have been met; and

a communication protocol section adapted to transmit DUT test or operation data from said FPGA through said fourth electrical signal interface with said communication interface to a computer adapted to analyze said data.

34. The method as in claim 33, wherein said DUT interface structure comprises an integrated circuit package receiving section adapted to receive a DUT comprising a 48-pin dual-inline package (DIP) system, wherein said communication interface comprises an RS232 adapter.

35. The method as in claim 34, wherein said integrated circuit package receiving section and said 48-pin DIP further comprises a shielding section adapted to prevent or mitigate damage from a radiation environment above a radiation threshold or heat exposure above a thermal threshold.

36. The method as in claim 34, further comprising a shield case adapted to encase said 48-pin DIP with a radiation shielding material.

37. The method as in claim 33, wherein said FPGA is further configured by said first or second plurality of machine readable instructions to multiply, scale, or adjust said timing signals supplied to said FPGA from said timing section.

38. The method as in claim 34, wherein said 48-pin DIP comprises a plurality of I/O elements configured to be grounds, one I/O configured to be a voltage input I/O, one I/O configured to be a receive I/O, one I/O configured to be a transmit I/O, and forty I/Os configured to be programmable I/Os.

39. The method as in claim 34, wherein said user selectable voltage switch comprises a supply voltage VDD I/O switch configured to enable said user to select one of said different voltages to one or more I/O elements or pins of said 48-pin DIP.

40. The method as in claim 33, wherein said adapter board further comprises an aperture, said first electrical signal interface is disposed outside and in proximity with said aperture, wherein said DUT interface structure is formed and positioned to position said DUT over said aperture in said first test structure.