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Compact electronics test system having user programmable device interfaces and on-board functions adapted for use in proximity to a radiation field

  • US 9,594,117 B2
  • Filed: 11/24/2014
  • Issued: 03/14/2017
  • Est. Priority Date: 11/22/2013
  • Status: Active Grant
First Claim
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1. A method comprising:

  • a first test structure comprising at least one first interface section and a second interface section, wherein said second interface section comprises an integrated circuit interface section comprising a plurality of programmable input and output elements, wherein said integrated circuit interface section is adapted to removably and electrically connect or release one or more said input and output elements with one or more input and output elements of a device under test (DUT), receive inputs and outputs from said DUT, process said inputs and outputs, and output processed data;

    a second test structure comprising;

    a third interface section adapted to selectively and removably electrically couple with said first interface section of said first structure;

    a power module adapted to modulate incoming power to different voltages from a power supply either on said second test structure or coupled with said second test structure, said power module supplies said different voltages to sections of said first and section test structure comprising one or more said plurality of programmable input and output elements through said first test structure via said third interface section to said first interface section;

    a user selectable voltage switch adapted to enable said user to select between said different voltages by manipulating said switch in different switch selection configurations;

    a programmable read only memory (PROM) adapted to store a first plurality of machine readable instructions and a first plurality of field programmable gate array (FPGA) configuration settings;

    a FPGA adapted to perform a plurality of FPGA operations comprising controlling said DUT and said programmable input and output elements through said third interface section, said FPGA is configured to couple with said PROM and receive said first plurality of machine readable instructions in an initial testing configuration and said first plurality of FPGA configuration settings, wherein said FPGA is further configured to create and store a second plurality of FPGA configuration settings on said PROM for later reload of said FPGA from said PROM, wherein said FPGA is also configured to selectively program said power module to select one of said different voltages and selectively configure and program one or more of said plurality of programmable input and output elements based on said first or second plurality of machine readable instructions, wherein said first and second plurality of machine readable instructions are configured to either reconfigure programmable logic elements within said FPGA or be executed by different programmable logic elements within said FPGA to perform said plurality of FPGA operations;

    an initial configuration load switch configured to transfer a copy of said first plurality of machine readable instructions to said FPGA to operate said FPGA in said first testing configuration operable to perform a first plurality of testing operations on said DUT;

    a timing signal generation section operable to supply one or different timing signals to said FPGA;

    a programming cable connection coupled with said FPGA adapted to electrically couple with a programming cable configured for receiving and conveying said first plurality of machine readable instructions or a second plurality of machine readable instructions to said FPGA;

    a plurality of light emitting diodes (LED) coupled with said FPGA adapted to indicate user programmable indication criteria settings associated with execution of said first or second plurality of machine readable instructions by said FPGA by outputting a different light emission associated with predetermined said indication criteria that have been met; and

    a communication protocol section adapted to transmit data from said FPGA through a communication signal data interface adaptor to a computer adapted to analyze said data.

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