Voltage regulator stabilization for operation with a wide range of output capacitances
First Claim
1. A voltage regulator comprising:
- a measurement circuit for generating a value representing a magnitude of a capacitance at an output node of the voltage regulator; and
a correction circuit for modifying, based on the value, a compensation circuit internal to the voltage regulator comprising resistance and capacitance and having a zero corresponding to a frequency substantially equal to (1/(2π
(the resistance being total resistance of internal wiring of an integrated ciruit and the equivalent series resistance of the output capacitor)(the capacitance being capacitance of the output capacitor)) the correction circuit modifying a closed-loop feedback circuit by increasing a frequency of the zero in the closed feedback loop of the voltage regulator by changing values of the resistance or the capacitance in the feedback loop to provide stability to the closed feedback loop.
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Accused Products
Abstract
A voltage regulator includes a measurement circuit for obtaining a value representing a magnitude of an output capacitance connected at an output node of the voltage regulator. A correction circuit in the voltage regulator modifies a compensation circuit internal to the voltage regulator based on the value. The modification of the compensation circuit is done to ensure that sufficient stability margins to accommodate the output capacitance are ensured for the main feedback loop in the voltage regulator. In an embodiment, a voltage proportional to the output capacitance is detected at start-up of the voltage regulator, and a corresponding binary signal is generated. The logic value of the binary signal is used to add or remove components and/or circuit portions in the compensation circuit to ensure stability. The voltage regulator is thus designed to support a wide range of output capacitance values.
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Citations
17 Claims
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1. A voltage regulator comprising:
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a measurement circuit for generating a value representing a magnitude of a capacitance at an output node of the voltage regulator; and a correction circuit for modifying, based on the value, a compensation circuit internal to the voltage regulator comprising resistance and capacitance and having a zero corresponding to a frequency substantially equal to (1/(2π
(the resistance being total resistance of internal wiring of an integrated ciruit and the equivalent series resistance of the output capacitor)(the capacitance being capacitance of the output capacitor)) the correction circuit modifying a closed-loop feedback circuit by increasing a frequency of the zero in the closed feedback loop of the voltage regulator by changing values of the resistance or the capacitance in the feedback loop to provide stability to the closed feedback loop. - View Dependent Claims (2, 3, 4)
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5. A voltage regulator comprising:
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a measurement circuit for generating a value representing a magnitude of an output capacitance connected at an output node of the voltage regulator; and a correction circuit for modifying, based on the value, a compensation circuit internal to the voltage regulator wherein the value representing the magnitude of the output capacitance is a binary signal, a first logic level of the binary signal corresponding to a magnitude of the output capacitance less than a threshold, and a second logic level of the binary signal corresponding to the magnitude of the output capacitance greater than the threshold, wherein the voltage regulator comprises a pass-transistor coupled in series with a voltage divider network containing a first resistor and second resistor, the voltage divider network being coupled in parallel with the output capacitor, wherein a path coupling the pass-transistor with the voltage divider network is associated with a first resistance, wherein a tap point of the voltage divider network is coupled to a first amplifier coupled to the pass-transistor to form a feedback path of a main feedback loop of the voltage regulator, wherein the first amplifier is comprised in a first cascade of amplifiers, wherein an output of the first cascade of amplifiers is coupled to the pass-transistor, the first cascade of amplifiers to amplify a difference of a reference voltage and a voltage at the junction of the first resistor and the second resistor, and to generate a correction voltage at an output node of the first amplifier, wherein the output of the first cascade of amplifiers is generated as a difference of a voltage at the tap point and the reference voltage. - View Dependent Claims (6, 7, 8, 9)
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10. A system comprising:
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an antenna to receive a signal on a wireless medium; an analog processor to process the signal and to generate a processed signal; an analog to digital converter (ADC) to receive the processed signal as input and to generate a plurality of digital values representing the processed signal; a processor to process the plurality of digital values; and a voltage regulator to receive power from a battery, and provide a regulated output voltage for the operation of each of the analog processor, ADC, and the processor, wherein, the voltage regulator comprises; a measurement circuit for generating a value representing a magnitude of a capacitance at an output node of the voltage regulator; and a correction circuit for modifying, based on the value, a compensation circuit internal to the voltage regulator comprising resistance and capacitance and having a zero corresponding to a frequency substantially equal to (1/(2π
(the resistance being total resistance of internal wiring of an integrated circuit and the equivalent series resistance of the output capacitor)(the capacitance being capacitance of the output capacitor)) the correction circuit modifying a closed-loop feedback circuit by increasing a frequency of the zero in the closed feedback loop of the voltage regulator by changing values of the resistance or the capacitance in the feedback loop to provide stability to the closed feedback loop. - View Dependent Claims (11)
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12. A system comprising:
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an antenna to receive a signal on a wireless medium; an analog processor to process the signal and to generate a processed signal; an analog to digital converter (ADC) to receive the processed signal as input and to generate a plurality of digital values representing the processed signal; a processor to process the plurality of digital values; and a voltage regulator to receive power from a battery, and provide a regulated output voltage for the operation of each of the analog processor, ADC, and the processor, wherein, the voltage regulator comprises; a measurement circuit for generating a value representing a magnitude of capacitance at an output node of the voltage regulator; and a correction circuit for modifying, based on the value, a compensation circuit internal to the voltage regulator wherein the value representing the magnitude of the capacitance at the output node is a binary signal, a first logic level of the binary signal corresponding to a magnitude of the output capacitance less than a threshold, and a second logic level of the binary signal corresponding to the magnitude of the output capacitance greater than the threshold, wherein the voltage regulator comprises a pass-transistor coupled in series with a voltage divider network containing a first resistor and second resistor, the voltage divider network being coupled in parallel with the output capacitor, wherein a path coupling the pass-transistor with the voltage divider network is associated with a first resistance, wherein a tap point of the voltage divider network is coupled to a first amplifier coupled to the pass-transistor to form a feedback path of a main feedback loop of the voltage regulator, wherein the first amplifier is comprised in a first cascade of amplifiers, wherein an output of the first cascade of amplifiers is coupled to the pass-transistor, the first cascade of amplifiers to amplify a difference of a reference voltage and a voltage at the junction of the first resistor and the second resistor, and to generate a correction voltage at an output node of the first amplifier, wherein the output of the first cascade of amplifiers is generated as a difference of a voltage at the tap point and the reference voltage. - View Dependent Claims (13, 14, 15, 16, 17)
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Specification