Computing platform with interface based error injection

• US 9,594,570 B2
• Filed: 11/21/2012
• Issued: 03/14/2017
• Est. Priority Date: 11/22/2011
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Kumar, Mohan, Jayakumar, Sarathy, Vargas, Jose Andy
• Primary Examiner(s): Mehrmanesh, Elmira
• Application Number:
  US13/977,625
• Publication Number:
  US 20140053024A1
• Time in Patent Office: 1,574 Days
• Field of Search: 714/41
• US Class Current: 1/1
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/28 Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 11/3024 where the computing system component is a central processing unit [CPU]
• CPC Class Codes: G06F 11/3409 for performance assessment
• CPC Class Codes: G06F 11/3447 Performance evaluation by modeling
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 11/3664 Environments for testing or debugging software
• CPC Class Codes: G06F 11/3672 Test management
• CPC Class Codes: G06F 11/3688 for test execution, e.g. scheduling of test suites
• CPC Class Codes: G06F 15/7871 Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
• CPC Class Codes: G06F 16/2282 Tablespace storage structures; Management thereof
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 2209/501 Performance criteria
• CPC Class Codes: G06F 9/22 : Microcontrol or microprogram arrangements
• CPC Class Codes: G06F 9/30098 : Register arrangements
• CPC Class Codes: G06F 9/3012 : Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/384 : Register renaming
• CPC Class Codes: G06F 9/44 : Arrangements for executing specific programs
• CPC Class Codes: G06F 9/4401 : Bootstrapping security arrangements therefor G06F21/57
• CPC Class Codes: G06F 9/4403 : Processor initialisation
• CPC Class Codes: G06F 9/4418 : Suspend and resume; Hibernate and awake
• CPC Class Codes: G06F 9/445 : Program loading or initiating bootstrapping G06F9/4401; security arrangements for program loading or initiating G06F21/57
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Described is a computing platform, which comprises: a non-volatile memory having a firmware boot program; and a CPU to execute the firmware boot program when the CPU is reset, the firmware boot program including instructions to create Power and Performance Measurement (PPM) interface data structures including an error injection table structure to provide error injection services to an OS.

Claims

1. A computing platform, comprising:

a non-volatile memory having a firmware boot program; and

a CPU to execute the firmware boot program when the CPU is reset, the firmware boot program including instructions to create Power and Performance Management (PPM) interface data structures including an error injection table structure to provide error injection services to an Operating System (OS), wherein the PPM interface data structures are associated with a PPM interface which comprises PPM registers, PPM firmware components, and PPM tables, and wherein the PPM interface is to implement a platform control channel (PCC) to communicate with PPM functionality of the OS and PPM hardware features, wherein the OS is configured to;

execute a first action to determine an error injection capability of a platform,

receive a first response that includes a first error injection table of the error injection table structure, the first error injection table identifying one or more standard error types supported by the platform and at least one platform defined error type supported by the platform,

choose, for injection, a first error type from among the one or more standard error types and the at least one platform defined error type, and

execute a second action to instruct the platform to begin an error injection operation using the first error type.

2. The computing platform of claim 1, in which the error injection table structure comprises a table with supported error injection actions.

3. The computing platform of claim 1, in which the error injection table structure comprises a table showing a layout of an injection instruction entry.

4. The computing platform of claim 1, in which the error injection table structure comprises a table showing instruction flags.

5. The computing platform of claim 1, wherein the OS is configured to:

in response to the first error injection table identifying the at least one platform defined error type supported by the platform, receive a second response that includes a second error injection table of the error injection table structure, the second error injection table defining the at least one platform defined error type and a data structure associated with the at least one platform defined error type.

6. The computing platform of claim 1, in which the error injection table structure comprises a table defining error injection status codes returned from GET COMMAND STATUS in accordance with an Advanced Configuration and Power Interface (ACPI) implementation.

7. The computing platform of claim 1, in which the error injection table structure comprises table listing error type codes returned from GET_ERROR TYPE in accordance with an Advanced Configuration and Power Interface (ACPI) implementation.

8. The computing platform of claim 7, in which the error injection table structure comprises a table showing a SET_ERROR_TYPE_WITH_ADDRESS data structure.

9. The computing platform claim 1, in which the OS is to inject an error through the PPM interface by sending a command through the PPM interface to inject the error and then triggering the error as a separate action.

10. An apparatus, comprising:

a first memory storage device having instructions including operating system (OS) Power and Performance Management (PPM) components for a PPM interface; and

a second memory storage device having instructions for a firmware boot program including firmware PPM components for the PPM interface, the OS and firmware PPM instructions, when executed, to establish the PPM interface between the OS and platform hardware, the PPM interface including an error injection data structure to enable the OS to cause an error into a desired hardware component, wherein the PPM interface comprises PPM registers and PPM tables, and wherein the PPM interface is to implement a platform control channel (PCC) to communicate with PPM functionality of the OS and PPM hardware features, and wherein the OS is configured to;

receive, from a platform, an identification of one or more standard error types supported by the platform and at least one platform defined error type supported by the platform,

choose a first error type from among the one or more standard error types and the at least one platform defined error type, and

instruct the platform to begin an error injection operation using the first error type.

11. The computing platform of claim 10, in which the error injection data structure is an Error Injection Table (EINJ) structure in accordance with an Advanced Configuration and Power Interface (ACPI) specification.

12. The computing platform of claim 11, wherein the EINJ structure is to inject hardware errors to the hardware computer platform independent of platform specific OS Power Management (OSPM) level software.

13. The computing platform of claim 12, wherein the EINJ structure comprises injection instruction entries which represent a primitive operation on an abstracted hardware register.

14. An apparatus, comprising:

a hardware computer platform having firmware including Advanced Configuration and Power Interface (ACPI) components to build an error injection data table (EINJ) structure for an ACPI interface, wherein the hardware computing platform is a smart-phone, and wherein the hardware computer platform is configured to;

receive, from an operating system (OS), a first request to determine an error injection capability of the hardware computer platform,

transmit a first response that includes a first error injection table, the first error injection table identifying one or more standard error types supported by the hardware computer platform and at least one platform defined error type supported by the hardware computer platform, wherein the OS chooses, for injection, a first error type from among the one or more standard error types and the at least one platform defined error type, and

receive a second request to begin an error injection operation using the first error type,

wherein the ACPI interface is to implement a platform control channel (PCC) to communicate with power and performance management functionality of the OS and power and performance management hardware features.

15. The apparatus of claim 14, wherein the EINJ structure is to inject hardware errors to the hardware computer platform independent of platform specific Operating System Power Management (OSPM) level software.

16. The apparatus of claim 15, wherein the EINJ structure comprises injection instruction entries which represent a primitive operation on an abstracted hardware register.

17. The apparatus of claim 16, wherein at least one of the injection instruction entries includes a description of a region in an injection hardware register and an injection instruction to be performed on the region.

18. The apparatus of claim 17, wherein the region is to describe a physical address of a register and a bit range that corresponds to a desired region of the register.

19. The apparatus of claim 18, wherein the bit range is a smallest set of consecutive bits that contains every bit in the register that is associated with the injection instruction.